module ledwalk(led,clk);
input clk;
output [7:0] led;
reg[7:0]led_out;
reg[25:0]buffer;
always@(posedge clk)
begin
buffer<=buffer+1'b1;
if(buffer==26'd25000000)
begin
led_out=led_out<<1;
if(led_out==8'b00000000)
led_out=8'b00000001;
end
end
assign led=led_out;
endmodule
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楼主
