2.5 Transmission-Acknowledge Register (CANTA)
Transmission-Acknowledge Register (CANTA) www.ti.com
If the message of mailbox n was sent successfully, the bit TA[n] is set. This also sets the GMIF0/GMIF1
(GIF0.15/GIF1.15) bit if the corresponding interrupt mask bit in the CANMIM register is set. The
GMIF0/GMIF1 bit initiates an interrupt.
The CPU resets the bits in CANTA by writing a 1. This also clears the interrupt if an interrupt has been
generated. Writing a 0 has no effect. If the CPU tries to reset the bit while the CAN tries to set it, the bit is
set. After power-up, all bits are cleared.
访问方式：LEGEND: RC = Read/Clear; ---- 读 或者 写1清0，
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