HDL程序为：
// First.v
module LED(
clk-48M,
RSTn,
LED
)；
input clk48M;
input RSTn;
output [3:0] LED;
reg [3:0] LED;
reg [22:0] cout;
always@(posedge clk48M or negedge RSTn)
begin
if(!RSTn)
begin
LED<=4'h8;
count<<=23'h0;
end
else
begin
count<=count+1;
if(count==23'hff_ff_ff)
begin
LED<=LED>>1;
count<=0;
if(LED==4'h0)
LED<=4'h8;
end
end
end
endmodule
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