**** Nested Vectored Interrupt Controller ****
/****************** Bit definition for NVIC_ISER register *******************/
#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
......
#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
----- 这都是什么的地址？（后面的同问）
/****************** Bit definition for NVIC_ICER register *******************/
#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
.......
/****************** Bit definition for NVIC_ISPR register *******************/
#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
......
/****************** Bit definition for NVIC_ICPR register *******************/
#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
..........
/****************** Bit definition for NVIC_IABR register *******************/
#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
.......
求赐教。。。。
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楼主
