[综合信息] 同样是做设计，他们的差别，不仅仅体现在技术水平上！

static void SetSysClock(void)

{

/******************************************************************************/

/*            PLL (clocked by HSE) used as System clock source                */

/******************************************************************************/

  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;

  

  /* Enable HSE */

  RCC->CR |= ((uint32_t)RCC_CR_HSEON);

 

  /* Wait till HSE is ready and if Time out is reached exit */

  do

  {

    HSEStatus = RCC->CR & RCC_CR_HSERDY;

    StartUpCounter++;

  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));



  if ((RCC->CR & RCC_CR_HSERDY) != RESET)

  {

    HSEStatus = (uint32_t)0x01;

  }

  else

  {

    HSEStatus = (uint32_t)0x00;

  }



  if (HSEStatus == (uint32_t)0x01)

  {

    /* Select regulator voltage output Scale 1 mode */

    RCC->APB1ENR |= RCC_APB1ENR_PWREN;

    PWR->CR |= PWR_CR_VOS;



    /* HCLK = SYSCLK / 1*/

    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;



#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx)      

    /* PCLK2 = HCLK / 2*/

    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;

    

    /* PCLK1 = HCLK / 4*/

    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;

#endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx */



#if defined (STM32F401xx)

    /* PCLK2 = HCLK / 2*/

    RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;

    

    /* PCLK1 = HCLK / 4*/

    RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;

#endif /* STM32F401xx */

   

    /* Configure the main PLL */

    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |

                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);



    /* Enable the main PLL */

    RCC->CR |= RCC_CR_PLLON;



    /* Wait till the main PLL is ready */

    while((RCC->CR & RCC_CR_PLLRDY) == 0)

    {

    }

   

#if defined (STM32F427_437xx) || defined (STM32F429_439xx)

    /* Enable the Over-drive to extend the clock frequency to 180 Mhz */

    PWR->CR |= PWR_CR_ODEN;

    while((PWR->CSR & PWR_CSR_ODRDY) == 0)

    {

    }

    PWR->CR |= PWR_CR_ODSWEN;

    while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)

    {

    }      

    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;

#endif /* STM32F427_437x || STM32F429_439xx  */



#if defined (STM32F40_41xxx)     

    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;

#endif /* STM32F40_41xxx  */



#if defined (STM32F401xx)

    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */

    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;

#endif /* STM32F401xx */



    /* Select the main PLL as system clock source */

    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));

    RCC->CFGR |= RCC_CFGR_SW_PLL;



    /* Wait till the main PLL is used as system clock source */

    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);

    {

    }

  }

  else

  { /* If HSE fails to start-up, the application will have wrong clock

         configuration. User can add here some code to deal with this error */

  }

}

======***前面没有注释***=======

static void SysClkConfig(void)

{

    stc_clk_sysclk_cfg_t    stcSysClkCfg;

    stc_clk_xtal_cfg_t      stcXtalCfg;

    stc_clk_mpll_cfg_t      stcMpllCfg;



    MEM_ZERO_STRUCT(stcSysClkCfg);

    MEM_ZERO_STRUCT(stcXtalCfg);

    MEM_ZERO_STRUCT(stcMpllCfg);



    /* Set bus clk div. */

    stcSysClkCfg.enHclkDiv  = ClkSysclkDiv1;  // 100MHz

    stcSysClkCfg.enExclkDiv = ClkSysclkDiv2;  // 50MHz

    stcSysClkCfg.enPclk0Div = ClkSysclkDiv1;  // 100MHz

    stcSysClkCfg.enPclk1Div = ClkSysclkDiv2;  // 50MHz

    stcSysClkCfg.enPclk2Div = ClkSysclkDiv4;  // 25MHz

    stcSysClkCfg.enPclk3Div = ClkSysclkDiv4;  // 25MHz

    stcSysClkCfg.enPclk4Div = ClkSysclkDiv2;  // 50MHz

    CLK_SysClkConfig(&stcSysClkCfg);



    /* Switch system clock source to MPLL. */

    /* Use Xtal as MPLL source. */

    stcXtalCfg.enMode        = ClkXtalModeOsc;

    stcXtalCfg.enDrv         = ClkXtalLowDrv;

    stcXtalCfg.enFastStartup = Enable;

    CLK_XtalConfig(&stcXtalCfg);

    CLK_XtalCmd(Enable);



    /* MPLL config. */

    stcMpllCfg.pllmDiv = 1ul;

    stcMpllCfg.plln    =50ul;

    stcMpllCfg.PllpDiv = 4ul;

    stcMpllCfg.PllqDiv = 4ul;

    stcMpllCfg.PllrDiv = 4ul;

    CLK_SetPllSource(ClkPllSrcXTAL);

    CLK_MpllConfig(&stcMpllCfg);



    /* flash read wait cycle setting */

    EFM_Unlock();

    EFM_SetLatency(5ul);

    EFM_Lock();



    /* Enable MPLL. */

    CLK_MpllCmd(Enable);



    /* Wait MPLL ready. */

    while(Set != CLK_GetFlagStatus(ClkFlagMPLLRdy))

    {

        ;

    }



    /* Switch system clock source to MPLL. */

    CLK_SetSysClkSource(CLKSysSrcMPLL);

}

    //初始化串口用端口 Initialize USART IO */

    PORT_SetFunc(USART_RX_PORT, USART_RX_PIN, USART_RX_FUNC, Disable);  //PortE

    PORT_SetFunc(USART_TX_PORT, USART_TX_PIN, USART_TX_FUNC, Disable);

 *******************************************************************************

 ** \brief   Set Port Pin function

 **

 ** \param   [in]  enPort               GPIO port index, This parameter can be

 **                                     any value of [url=home.php?mod=space&uid=144993]@ref[/url] en_port_t

 ** \param   [in]  u16Pin               GPIO pin index, This parameter can be

 **                                     any value of @ref en_pin_t

 ** \param   [in]  enFuncSel            Function selection, This parameter can be

 **                                     any value of @ref en_port_func_t

 **

 ** \param   [in] enSubFunc             The new state of the gpio sub-function.

 ** \arg     Enable                     Enable.

 ** \arg     Disable                    Disable.

 **

 ** \retval  Ok                         Set successful to corresponding pins

 **

 ******************************************************************************/

en_result_t PORT_SetFunc(en_port_t enPort, uint16_t u16Pin, en_port_func_t enFuncSel,  \

                  en_functional_state_t enSubFunc)

{

en_result_t PORT_SetFunc (...)

{

    for (u8PinPos = 0u; u8PinPos < 16u; u8PinPos ++)

    {

        if (u16Pin & (uint16_t)(1ul<<u8PinPos))

        {

            PFSRx = (stc_port_pfsr_field_t *)((uint32_t)(&M4_PORT->PFSRA0) \

                    + 0x40ul * enPort + 0x4ul * u8PinPos);



            /* main function setting */

            PFSRx->FSEL = enFuncSel;  //功能选择寄存器（PFSRxy）



            /* sub function enable setting */

            PFSRx->BFE = (Enable == enSubFunc ? Enable : Disable);

        }

    }

}