[应用相关] SPI应用和作用

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 楼主| 慢动作 发表于 2024-4-30 21:56 | 显示全部楼层 |阅读模式
ce, TI, TE, spi, pi
Spl Concept
SPI Interface
SPI Clock Polarity and Phase
SPI Topology Independent slave configuration
SPI Advantages
SPI Disadvantages
SPI Variant
1. Spl Concept
A synchronous serial communication interface
Used for short distance communication, primarily in embedded systems
Developed by Motorola in the mid 1980s
Communicate in full duplex mode using a single master multiple slave architecture
The master originates the frame for reading and writing
Multiple slave devices are supported through individual slave select(SS)lines

 楼主| 慢动作 发表于 2024-4-30 21:56 | 显示全部楼层
SPI Interface
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 楼主| 慢动作 发表于 2024-4-30 21:57 | 显示全部楼层
SPI Clock Polarity and Phase
660046630f8aae495c.png
 楼主| 慢动作 发表于 2024-4-30 21:57 | 显示全部楼层
SPI Topology Independent slave configuration
640496630f8b836d73.png
 楼主| 慢动作 发表于 2024-4-30 21:57 | 显示全部楼层
SPI Advantages
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 楼主| 慢动作 发表于 2024-4-30 21:57 | 显示全部楼层
SPI Disadvantages
Requires more pins on IC packages than PC, even in the three-wire variant
No in-band addressing; out-of-band chip select signals are required on shared buses
No hardware flow control by the slave
No hardware slave acknowledgment
Typically supports only one master device
No error-checking protocol is defined
Only handles short distances compared to RS-232, RS-485, or Can-bus
Many existing variations
 楼主| 慢动作 发表于 2024-4-30 21:57 | 显示全部楼层
SPI Variant
Three wire serial bus

Uses single bidirectional data line(SSO)instead of two lines(Mosl and MISO)
Restricted to a half duplex mode
Used for lower performance parts such as small EEPROMS sensors and Microwire
Dual SPI: A half-duplex configuration to send two bits per clock cycle

The Mosl line becomes SIO0 and carries even bits
The MISO line becomes Slo1 and carries odd bits
Data is still transmitted msbit-first
Slo1 carries bits 7, 5, 3 and 1 of each byte
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