Stellamar 公司的数字ADC采用Xilinx公司的 XC3S400AN FPGA,平均功耗低50%,面积低50%,非常低的工作电压,高达14位的有效位,14位500Hz的SNR为90dB,数字典输出,数字测试,过采样,不会丢失码,极低的失调漂移,能用在苛刻的环境.目标应用在语音,消费类和工业中的传感器,低功率手提设备以及军事,空间和航空航天.本文介绍了数字ADC主要特性,数字ADC音频评估板框架图,电路图和材料清单.
The Digital ADC is a digital core which provides analog functionality with all the benefits of a digital design process: shorter design cycles, lower risk, established design and layout tools, digital test methodology, and portability across process technologies.
The design is implemented with a small number of digital gates and only an LVDS input cell, a digital output cell and a handful of passive external components
The ADC provides up to 12 effective bits and up to 15 kHz of bandwidth making it ideal fit for both low frequency sensors and high-quality voice.
The benefits of the digital implementation include low voltage and low power process technologies where it excels in portable applications.
Alternative digital process technologies enable the Digital ADC to be used in high reliability and radiation hard environments where analog implementations are problematic.
数字ADC主要特性:
On average 50% less power1
On average 68% smaller area1
Very low supply voltages
Up to 14 effective bits
Bandwidth
o 14 bits, 500 Hz with SNR 90 dB
o 12 bits, 4 kHz with SNR 72 dB
o 12 bits, 15 kHz with SNR 68 dB
Process Technology Independent
Digital Layout
Digital Testing
Oversampling
No missing codes
Extremely low offset drift
Suitable for Rad-Hard environments |
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