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菜农对DSP开发板Study-2812增强版的改动说明<br /><br />雁塔菜农HotPower@126.com 2008.5.8 于雁塔菜地<br /><br />1.CPLD的改动<br />对光盘内的Code-F2812Ex21_HDL2DEV2812.V进行了大改动<br />a.加入8个键盘测试<br />b.改进LCD的访问不好的习惯<br />c.改进74hc595的锁存信号为一次完成脉冲的发送且带密码访问<br />d.增加CPLD的版本号或密码的访问及动态改写<br />e.整理了已完成例程的Verilog语言规范,但实在不愿改写管脚不良的定义<br /><br />2.改写或增加CMD文件<br /><br />对F2812_EzDSP_RAM_lnk.cmd内的<br />PRAMH0 : origin = 0x3F8002, length = 0x000FFE<br />改写为:<br />PRAMH0 : origin = 0x3F8002, length = 0x001FFE<br /><br />3.增加F2812_UserVariableDefs.cmd文件<br /><br />4.增加F2812_UserVariableDefs.cpp文件<br /><br />5.完整可用于实战的例程<br />由于开始建立工程时第1个例程是LCD,所以就起名LCD_DEMO<br />目前抽空完成的例程主要有:<br />LCD,SPI,TIMER,INT,KEY,LED,SCI,ADC等<br /><br />6.非典再现<br /><br />改写DSP281x_Adc.h,得到2种访问方式,不破坏原TI之习惯<br /><br />struct ADC_REGS {<br /> union ADCTRL1_REG ADCTRL1; // ADC Control 1<br /> union ADCTRL2_REG ADCTRL2; // ADC Control 2<br /> union ADCMAXCONV_REG ADCMAXCONV; // Max conversions<br /> union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1<br /> union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2<br /> union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3<br /> union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4<br /> union ADCASEQSR_REG ADCASEQSR; // Autosequence status register<br /> Uint16 ADCRESULT[16];<br />/* <br /> Uint16 ADCRESULT0; // Conversion Result Buffer 0<br /> Uint16 ADCRESULT1; // Conversion Result Buffer 1<br /> Uint16 ADCRESULT2; // Conversion Result Buffer 2<br /> Uint16 ADCRESULT3; // Conversion Result Buffer 3<br /> Uint16 ADCRESULT4; // Conversion Result Buffer 4<br /> Uint16 ADCRESULT5; // Conversion Result Buffer 5<br /> Uint16 ADCRESULT6; // Conversion Result Buffer 6<br /> Uint16 ADCRESULT7; // Conversion Result Buffer 7<br /> Uint16 ADCRESULT8; // Conversion Result Buffer 8<br /> Uint16 ADCRESULT9; // Conversion Result Buffer 9<br /> Uint16 ADCRESULT10; // Conversion Result Buffer 10<br /> Uint16 ADCRESULT11; // Conversion Result Buffer 11<br /> Uint16 ADCRESULT12; // Conversion Result Buffer 12<br /> Uint16 ADCRESULT13; // Conversion Result Buffer 13<br /> Uint16 ADCRESULT14; // Conversion Result Buffer 14<br /> Uint16 ADCRESULT15; // Conversion Result Buffer 15<br />*/ <br /> union ADCTRL3_REG ADCTRL3; // ADC Control 3<br /> union ADCST_REG ADCST; // ADC Status Register<br />};<br /><br />#define ADCRESULT0 ADCRESULT[0]<br />#define ADCRESULT1 ADCRESULT[1]<br />#define ADCRESULT2 ADCRESULT[2]<br />#define ADCRESULT3 ADCRESULT[3]<br />#define ADCRESULT4 ADCRESULT[4]<br />#define ADCRESULT5 ADCRESULT[5]<br />#define ADCRESULT6 ADCRESULT[6]<br />#define ADCRESULT7 ADCRESULT[7]<br />#define ADCRESULT8 ADCRESULT[8]<br />#define ADCRESULT9 ADCRESULT[9]<br />#define ADCRESULT10 ADCRESULT[10]<br />#define ADCRESULT11 ADCRESULT[11]<br />#define ADCRESULT12 ADCRESULT[12]<br />#define ADCRESULT13 ADCRESULT[13]<br />#define ADCRESULT14 ADCRESULT[14]<br />#define ADCRESULT15 ADCRESULT[15]<br /><br />应用例如:<br /> for (int i = 0; i < sizeof(Result); i ++)<br /> {<br /> Result = 0;<br /> }<br /> for (int i = 0; i < 16; i ++)<br /> {<br /> AdcRegs.ADCRESULT = 0;<br /> }<br /> AdcRegs.ADCRESULT[0] = 0;<br /> AdcRegs.ADCRESULT0 = 0;<br /> AdcRegs.ADCRESULT[1] = 0;<br /> AdcRegs.ADCRESULT1 = 0;<br /><br />此思路可在其他类型一致连续的结构中都可利用~~~<br />例如：<br />在DSP281x_ECan.h中<br /><br />struct ECAN_MBOXES {<br /> struct MBOX MBOX0;<br />//..........................<br /> struct MBOX MBOX31;<br />};<br /><br />改为:<br />struct ECAN_MBOXES {<br /> struct MBOX MBOXS[32];<br />};<br /><br />#define MBOX0 MBOXS[0] <br />//.......................<br />#define MBOX31 MBOXS[31] <br /><br /><br />在DSP281x_SysCtrl.h中<br />/* Password locations */<br />struct CSM_PWL {<br /> Uint16 PSWD0; // PSWD bits 15-0<br /> Uint16 PSWD1; // PSWD bits 31-16<br /> Uint16 PSWD2; // PSWD bits 47-32<br /> Uint16 PSWD3; // PSWD bits 63-48<br /> Uint16 PSWD4; // PSWD bits 79-64<br /> Uint16 PSWD5; // PSWD bits 95-80<br /> Uint16 PSWD6; // PSWD bits 111-96<br /> Uint16 PSWD7; // PSWD bits 127-112<br />};<br /><br />可改为:<br />/* Password locations */<br />struct CSM_PWL {<br /> Uint16 PSWD[8]; // PSWD bits 15-0<br />};<br /><br />#define PSWD0 PSWD[0]<br />//...................<br />#define PSWD7 PSWD[7]<br /><br />/* CSM Register File */<br />struct CSM_REGS {<br /> Uint16 KEY0; // KEY reg bits 15-0<br /> Uint16 KEY1; // KEY reg bits 31-16<br /> Uint16 KEY2; // KEY reg bits 47-32<br /> Uint16 KEY3; // KEY reg bits 63-48<br /> Uint16 KEY4; // KEY reg bits 79-64<br /> Uint16 KEY5; // KEY reg bits 95-80<br /> Uint16 KEY6; // KEY reg bits 111-96<br /> Uint16 KEY7; // KEY reg bits 127-112<br /> Uint16 rsvd1; // reserved<br /> Uint16 rsvd2; // reserved<br /> Uint16 rsvd3; // reserved<br /> Uint16 rsvd4; // reserved<br /> Uint16 rsvd5; // reserved<br /> Uint16 rsvd6; // reserved<br /> Uint16 rsvd7; // reserved<br /> union CSMSCR_REG CSMSCR; // CSM Status & Control register<br />};<br /><br />改为:<br />struct CSM_REGS {<br /> Uint16 KEY[8];<br />//................................. <br />};<br /><br />#define KEY0 KEY[0]<br />//...........................<br />#define KEY7 KEY[7]<br /><br /><img src="https://bbs.21ic.com/upfiles/img/20076/200762319329207.gif"><br /><br /><img src="https://bbs.21ic.com/upfiles/img/20076/200762319342387.gif"><br /><br /><img src="https://bbs.21ic.com/upfiles/img/20076/200762319356739.gif"><br /> |
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