如果CPU和CLA同时访问一个shared RAM区域，是要遵循下面的仲裁机制的，即先后顺序，
•CLA to CPU Message RAM: Priority of accesses are (highest priority first):
1.CLA write
2.CPU debug write
3.CPU data read, program read, CPU debug read
4.CLA data read
•CPU to CLA Message RAM: Priority of accesses are (highest priority first):
1.CLA read
2.CPU data write, program write, CPU debug write
3.CPU data read, CPU debug read
4.CPU program read
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