•CLA to CPU Message RAM: Priority of accesses are (highest priority first):
1.CLA write
2.CPU debug write
3.CPU data read, program read, CPU debug read
4.CLA data read
•CPU to CLA Message RAM: Priority of accesses are (highest priority first):
1.CLA read
2.CPU data write, program write, CPU debug write
3.CPU data read, CPU debug read
4.CPU program read