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Located in Shenzhen<br /><br />Primary Responsibility<br /><br />Be responsible for physical design of large, complex CMOS chips. Tasks including floor plan, partition, power routing, place & route, static timing analysis, DRC/LVS and other physical verification. <br />Work with customer design team early in design phase to define good design strategies. <br />Provide feedback and work closely with product development teams to improve design flow. <br />Coordinate and work with world wide design teams to ensure on time delivery of design results. <br /><br />Qualifications<br /><br />Bachelor degree or above in EE major <br />Minimum 3 year related experience with a solid IC design and EDA tool background <br />Solid understanding of deep sub-micron signal integrity issues such a cross-talk, IR drop, etc <br />Capable of handling multiple tasks at one time <br />Experienced in place & route, static timing analysis, synthesis <br />Extensive knowledge and experience with Magma, or Synopsys place & route tools <br />Extensive knowledge and experience with Synopsys DC, PT and PTSI tool <br />Experience with Perl, tcl scripting <br />Good customer communication skill is a must <br />Good command of English <br />Good command of Unix <br /><br />联系邮箱: rabby2003@tom.com |
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