下面的代码谁给我大概描述一下
reg clk_12m,clk_6m,clk_3m,clk_2m,clk_1m,
clk_512k,clk_256k,clk_128k,clk_64k,clk_32k,
clk_16k,clk_8k,clk_4k,clk_2k,clk_1k;
reg rst_count1,rst_count2,rst_count3,rst_count4;
reg[3:0] counter;
reg timer_flag=1'b0;
reg[3:0] pwr48v_good_count1,pwr48v_good_count2,pwr48v_good_count3,pwr48v_good_count4;
//generate clk
always @ (posedge CPLD_CLK_25M) clk_12m <= ~clk_12m;
always @ (posedge clk_12m) clk_6m <= ~clk_6m;
always @ (posedge clk_6m) clk_3m <= ~clk_3m;
always @ (posedge clk_3m) clk_2m <= ~clk_2m;
always @ (posedge clk_2m) clk_1m <= ~clk_1m;
always @ (posedge clk_1m) clk_512k <= ~clk_512k;
always @ (posedge clk_512k) clk_256k <= ~clk_256k;
always @ (posedge clk_256k) clk_128k <= ~clk_128k;
always @ (posedge clk_128k) clk_64k <= ~clk_64k;
always @ (posedge clk_64k) clk_32k <= ~clk_32k;
always @ (posedge clk_32k) clk_16k <= ~clk_16k;
always @ (posedge clk_16k) clk_8k <= ~clk_8k;
always @ (posedge clk_8k) clk_4k <= ~clk_4k;
always @ (posedge clk_4k) clk_2k <= ~clk_2k;
always @ (posedge clk_2k) clk_1k <= ~clk_1k;
always@(posedge clk_1k)
begin
if(!EN_VCC12V)
begin
counter<=4'b0000;
timer_flag<=1'b0;
end
else begin
if(counter!=4'b1111)
begin
counter<=counter+1'b1;
timer_flag<=1'b0;
end
else begin
timer_flag<=1'b1;
counter<=4'b1111;
end
end
end |
|
楼主
