本帖最后由 qq512452440 于 2015-10-25 17:43 编辑
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clk_div:U1|clk_25M_1" as buffer
Info: Detected ripple clock "clk_div:U1|cout2" as buffer
Info: Detected ripple clock "clk_div:U1|cout1" as buffer
Info: Detected gated clock "clk_div:U1|clk_10M" as buffer
Warning: Found 12 output pins without output pin load capacitance assignment
Info: Pin "o_hin" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "o_lin" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "o_dvdt" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led_out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led_out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led_out[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led_out[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "led_out[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "wrong_state" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Info: Pin "state_ok" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "rst" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.
Warning (13310): Register "signal:U3|signal_LIN_HIN_invert:U4|hin_out_4" is converted into an equivalent circuit using register "signal:U3|signal_LIN_HIN_invert:U4|hin_out_4~_emulated" and latch "signal:U3|signal_LIN_HIN_invert:U4|hin_out_4~latch"
Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "signal:U3|signal_LIN_HIN_invert:U4|hin_out_4~latch" is a latch原先用的是ep1c3t144c8n ，可以使用，后来FPGA坏了，换成了EP2C5t144c8n，无法输出波形
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