MSP430F5529的P6.0adc采样值值不是0就是1

只看该作者 · 2018-7-15 09:57

四通道采集，其他通道可以，P6.0采集结果低电平为0，高电平为1，是不是我手里的板子有问题，还是说这个通道不同于其他通道，需要特殊配置？
#include <msp430.h>
#define Num_of_Results 8
volatile unsigned int A0results[Num_of_Results];
volatile unsigned int A1results[Num_of_Results];
volatile unsigned int A2results[Num_of_Results];
volatile unsigned int A3results[Num_of_Results];

int main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                // Stop WDT
   P6DIR = 0x00;
   P6SEL = 0x0F;                            // Enable A/D channel inputs
   ADC12CTL0 = ADC12ON+ADC12MSC+ADC12SHT0_3; // Turn on ADC12, extend sampling time    保持32个周期                                     // to avoid overflow of results
   ADC12CTL1 = ADC12SHP+ADC12CONSEQ_3;    // Use sampling timer, repeated sequence
   ADC12CTL2 |= ADC12RES_3;                //12位  13个时钟  DOC 1Mhz    4.2915*10e-5
   ADC12MCTL0 = ADC12INCH_0;                // ref+=AVcc, channel = A0
   ADC12MCTL1 = ADC12INCH_1;                // ref+=AVcc, channel = A1
   ADC12MCTL2 = ADC12INCH_2;                // ref+=AVcc, channel = A2
   ADC12MCTL3 = ADC12INCH_3+ADC12EOS;       // ref+=AVcc, channel = A3, end seq.
   ADC12IE = 0x08;                         // Enable ADC12IFG.3
   ADC12CTL0 |= ADC12ENC;                   // Enable conversions
   ADC12CTL0 |= ADC12SC;                   // Start convn - software trigger
   _EINT();

  while (1)
  {
ADC12CTL0 |= ADC12SC;                // Start sampling/conversion

//__bis_SR_register(LPM0_bits + GIE);    // LPM0, ADC12_ISR will force exit
//__no_operation();                      // For debugger
  }
}

#pragma vector=ADC12_VECTOR
__interrupt void ADC12ISR (void)
{ //unsigned char a;
  static unsigned int index = 0;

  switch(__even_in_range(ADC12IV,34))
  {
  case  0: break;                         // Vector  0:  No interrupt
  case  2: break;                         // Vector  2:  ADC overflow
  case  4: break;                         // Vector  4:  ADC timing overflow
  case  6: break;                         // Vector  6:  ADC12IFG0
  case  8: break;                         // Vector  8:  ADC12IFG1
  case 10: break;                         // Vector 10:  ADC12IFG2
  case 12:                               // Vector 12:  ADC12IFG3
A0results[index] = ADC12MEM0;          // Move A0 results, IFG is cleared          dianya
A1results[index] = ADC12MEM1;          // Move A1 results, IFG is cleared
A2results[index] = ADC12MEM2;          // Move A2 results, IFG is cleared
A3results[index] = ADC12MEM3;          // Move A3 results, IFG is cleared
index++;                               // Increment results index, modulo; Set Breakpoint1 here

if (index == 8)
{
   (index = 0);
}
}
}