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module Ram(RamAddrH, RamAddrL, RamAddrMSB, RamData, <br /> RamWR, RamRD, RamCS, McuData, McuWR, McuRD, McuRS, xck);<br /><br />output RamWR; // cpld 与 ram 的写信号<br />output RamRD; // cpld 与 ram 的读信号<br />output RamCS; // cpld 与 ram 的片选信号<br /><br /><br /><br />initial<br />begin<br /> RamWR=1'b1; <br /> RamRD=1'b1;<br /> RamCS='b0;<br /> RamAddrMSB=1'b0;<br />end<br /><br />//////////////////////////////////////////////////<br />编译是出现如下错误<br />Error: Verilog HDL Procedural Assignment error at Ram.v(30): illegal Procedural Assignment to nonregister data type "RamWR"<br />Error: Verilog HDL Procedural Assignment error at Ram.v(31): illegal Procedural Assignment to nonregister data type "RamRD"<br />Error: Verilog HDL Procedural Assignment error at Ram.v(32): illegal Procedural Assignment to nonregister data type "RamCS"<br />Error: Verilog HDL Procedural Assignment error at Ram.v(34): illegal Procedural Assignment to nonregister data type "RamAddrMSB"<br /><br /><br />这是为什么啊? |
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