问答

[i=s] 本帖最后由 a438338076 于 2021-4-30 00:46 编辑 [/i] 本人看了两天，自己写了几遍，还是出错，希望有大神来帮我解决下这个仿真问题module delay( input clk ,//时钟信号 input rst_n ,//全局复位信号，低有效 input din ,//输入信号 input [7:0] dly_data , output reg dout ); wire add_cnt ; wire end_cnt ; reg [7:0] dly_data_reg ; reg [2:0] din_ff ; reg pos_flag ; reg neg_flag ; reg [7:0] cnt ; always @(posedge clk or negedge rst_n)begin if(rst_n == 1'b0)begin dly_data_reg <= 'd0; end else begin dly_data_reg <= dly_data; end end always @(posedge clk)begin din_ff <= {din_ff[1:0],din}; end //上升沿 always @(posedge clk or negedge rst_n)begin if(rst_n == 1'b0)begin pos_flag <= 1'b0; end else if(end_cnt)begin pos_flag <= 1'b0; end else if(pos_flag == 1'b0 &&din_ff[2:1] == 2'b01)begin pos_flag <= 1'b1; end end //下降沿 always @(posedge clk or negedge rst_n)begin if(rst_n == 1'b0)begin neg_flag <= 1'b0; end else if(end_cnt)begin neg_flag <= 1'b0; end else if(neg_flag == 1'b0 &&din_ff[2:1] == 2'b10)begin neg_flag <= 1'b1; end end //延迟值 always @(posedge clk or negedge rst_n)begin if(!rst_n)begin cnt <= 0; end else if(add_cnt)begin if(end_cnt) cnt <= 0; else cnt <= cnt + 1'b1; end end assign add_cnt = pos_flag || neg_flag; assign end_cnt = add_cnt && cnt == dly_data_reg -1; always @(posedge clk or negedge rst_n)begin if(rst_n == 1'b0)begin dout <= 1'b0; end else if(pos_flag && end_cnt)begin//上升沿来了 dout <= 1'b1; end else if(neg_flag && end_cnt)begin//下降沿来了 dout <= 1'b0; end end endmodule