问答

我在RA2上使用电平变中断，现在的问题是IO上电平发生变化后不没有中断信号产生，不知道哪里出问题了，{ _TRISA2 = 1; _CNPUA2 = 1; _CNPDA2 = 0; CNCONA = 0x8800; CNEN0A = 0x0004;//RA2 CNEN1A = 0x0004;//下降沿 CNFA = 0x0000; IFS0bits.CNAIF = 0;//清除中断标志 IEC0bits.CNAIE = 1; }

[i=s] 本帖最后由 a438338076 于 2021-4-30 00:46 编辑 [/i] 本人看了两天，自己写了几遍，还是出错，希望有大神来帮我解决下这个仿真问题module delay( input clk ,//时钟信号 input rst_n ,//全局复位信号，低有效 input din ,//输入信号 input [7:0] dly_data , output reg dout ); wire add_cnt ; wire end_cnt ; reg [7:0] dly_data_reg ; reg [2:0] din_ff ; reg pos_flag ; reg neg_flag ; reg [7:0] cnt ; always @(posedge clk or negedge rst_n)begin if(rst_n == 1'b0)begin dly_data_reg <= 'd0; end else begin dly_data_reg <= dly_data; end end always @(posedge clk)begin din_ff <= {din_ff[1:0],din}; end //上升沿 always @(posedge clk or negedge rst_n)begin if(rst_n == 1'b0)begin pos_flag <= 1'b0; end else if(end_cnt)begin pos_flag <= 1'b0; end else if(pos_flag == 1'b0 &&din_ff[2:1] == 2'b01)begin pos_flag <= 1'b1; end end //下降沿 always @(posedge clk or negedge rst_n)begin if(rst_n == 1'b0)begin neg_flag <= 1'b0; end else if(end_cnt)begin neg_flag <= 1'b0; end else if(neg_flag == 1'b0 &&din_ff[2:1] == 2'b10)begin neg_flag <= 1'b1; end end //延迟值 always @(posedge clk or negedge rst_n)begin if(!rst_n)begin cnt <= 0; end else if(add_cnt)begin if(end_cnt) cnt <= 0; else cnt <= cnt + 1'b1; end end assign add_cnt = pos_flag || neg_flag; assign end_cnt = add_cnt && cnt == dly_data_reg -1; always @(posedge clk or negedge rst_n)begin if(rst_n == 1'b0)begin dout <= 1'b0; end else if(pos_flag && end_cnt)begin//上升沿来了 dout <= 1'b1; end else if(neg_flag && end_cnt)begin//下降沿来了 dout <= 1'b0; end end endmodule

我编写了两个文件，配置了输出口，，LASER_PWM 始终输出不了波形，请问下，这个是什么原因呀？modesiem仿真是有波形输出的//////////////-------PWM.V 文件 `timescale 1 ns / 1 ps module pwm( input rsn, input clk, input [15:0]pwm_counter, input [15:0]pwm_duty, output pwm_out ); //reg[15:0]pwm_counter; //reg [15:0]pwm_duty; reg [15:0]counter=16'd0; reg pwm_out_r; always@(posedge clk or negedge rsn) //begin if(!rsn) begin counter <= 16'd0; end else begin if(counter >= pwm_counter)counter <= 16'd0; else counter <= counter + 1'd1; end // end always@(posedge clk or negedge rsn) if(!rsn) begin pwm_out_r <= 1'd0; end else if(counter>=pwm_duty) pwm_out_r<=1'b0; else pwm_out_r<=1'b1; //wire pwm_out; assign pwm_out = pwm_out_r;//((counter > pwm_duty) ? 1'd0 : 1'd1); endmodule ////// top_indepen.v 文件 //-------------------------Timescale----------------------------// `timescale 1 ns / 1 ps //--------------------FSMC_SIG---------------------// module FSMC_INDEP( FPGA_CLK, //鏉堟挸鍙嗛弶鑳祰閺呰埖灏烥PGA_CLK,25M FPGA_LEDR, FPGA_LEDG, FPGA_LEDB, WR, //FSMC閸愭瑤淇婇崣 RD, //FSMC鐠囪淇婇崣 CS0, //FSMC閻楀洭鈧 A, //FSMC閸︽澘**冮幀鑽ゅ殠 DB, //FSMC閺佺増宓侀幀鑽ゅ殠 NADV, //FSMC閻ㄥ嚞ADV //LASER PWM LASER_PWM, //interpn_exti Interp_ex, testclk, testclk_100, testclk_50, FPGA_KEY ); input FPGA_KEY; input FPGA_CLK,NADV; input WR,RD,CS0; inout [15:0]DB; input [24:16]A; output FPGA_LEDB,FPGA_LEDG,FPGA_LEDR; assign FPGA_LEDR = 1'd1; assign FPGA_LEDG = 1'd0; assign FPGA_LEDB = 1'd1; output LASER_PWM; output Interp_ex,testclk,testclk_100,testclk_50; //-------------------------MY_PLL-------------------------------// wire PLL_100M; wire PLL_8M; wire PLL_50M; wire PLL_12_5M; reg LaserCtrl1; reg [15:0] dbPower1;//閸旂喓宸 閸楃姷鈹栧В reg [15:0]dbQFreq1;//妫版垹宸 reg [15:0]counter; initial begin dbQFreq1 <= 16'd106; dbPower1 <= 16'd53; LaserCtrl1 <= 1'd1; end MY_PLL U1( .inclk0(FPGA_CLK), .c0(PLL_100M), .c1(PLL_50M), .c2(PLL_8M), .c3(PLL_12_5M) );// //------------------------RST_Ctrl-----------------------------// wire RST_n; RST_Ctrl U2( .FPGA_CLK(FPGA_CLK), .RST_n(RST_n) ); //娓氬瀵睷ST_Ctrl濡€虫健,鏉堟挸鍤崗銊ョ湰婢跺秳缍呮穱鈥冲娇RST_n pwm U5( .rsn(RST_n), .clk(PLL_8M), .pwm_counter(dbQFreq1), .pwm_duty(dbPower1),//閸旂喓宸 .pwm_out(LASER_PWM) ); endmodule