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21ic问答首页 - HT32F57341仿真时出现这个,编译无错

仿真 编译 TE UG BUG

HT32F57341仿真时出现这个,编译无错

rocHP2021-03-17

Load "C:\\Users\\hppen\\Desktop\\HT32Fxx\\example\\GPIO\\InputOutput\\MDK_ARMv5\\Obj\\HT32.axf"
Cannot access Memory (@ 0x00000000, Write, Acc Size: 4 Byte)
Cannot access Memory (@ 0x00001000, Write, Acc Size: 4 Byte)
*** error 57: illegal address (0x00001000)
Include "C:\\Users\\hppen\\Desktop\\HT32Fxx\\example\\GPIO\\InputOutput\\MDK_ARMv5\\HT32F5xxxx_01_DebugSupport.ini"
/*----------------------------------------------------------------------------------------------------------*/
/* Holtek Semiconductor Inc.                                                                                */
/*                                                                                                          */
/* Copyright (C) Holtek Semiconductor Inc.                                                                  */
/* All rights reserved.                                                                                     */
/*                                                                                                          */
/*------------------------------------------------------------------------------------------------------------
  File Name        : HT32F5xxxx_01_DebugSupport.ini
  Version          : V1.03
  Date             : 2019-07-08
  Description      : Debug Support Initialization file.
------------------------------------------------------------------------------------------------------------*/

// Supported Device
// ========================================
// HT32F5xxxx

// <<< Use Configuration Wizard in Context Menu >>>
FUNC void DebugSupport (void)
{

//  <e0.0> Configure MCU Debug Control Register
//  <o2.0>  Debug Sleep Mode (DBSLP)
//          <i> LDO = On, FCLK = On, and HCLK = On in Sleep mode
//  <o2.1>  Debug Deep-Sleep Mode 1 (DBDSLP1)
//          <i> LDO = On, FCLK = On, and HCLK = On in Deep-Sleep mode 1
//  <o2.14> Debug Deep-Sleep Mode 2 (DBDSLP2)
//          <i> LDO = On, FCLK = On, and HCLK = On in Deep-Sleep mode 2
//  <o2.2>  Debug Power-Down Mode (DBPD)
//          <i> LDO = On, FCLK = On, and HCLK = On in Power-Down mode
//  <o2.3>  WDT Debug Mode Enable (DBWDT)
//          <i> WDT Timer counter is stopped when the core is halted
//  <o2.4>  MCTM0 Debug Mode Enable (DBMCTM0)
//          <i> MCTM0 Timer counter is stopped when the core is halted
//  <o2.6>  GPTM0 Debug Mode Enable (DBGPTM0)
//          <i> GPTM0 Timer counter is stopped when the core is halted
//  <o2.7>  GPTM1 Debug Mode Enable (DBGPTM1)
//          <i> GPTM1 Timer counter is stopped when the core is halted
//  <o2.8>  USART0 Debug Mode Enable (DBUSART0)
//          <i> USART0 Rx FIFO timeout counter is stopped when the core is halted
//  <o2.9>  USART1 Debug Mode Enable (DBUSART1)
//          <i> USART1 Rx FIFO timeout counter is stopped when the core is halted
//  <o2.18> UART0 Debug Mode Enable (DBUART0)
//          <i> UART0 Rx FIFO timeout counter is stopped when the core is halted
//  <o2.19> UART1 Debug Mode Enable (DBUART1)
//          <i> UART1 Rx FIFO timeout counter is stopped when the core is halted
//  <o2.26> UART2 Debug Mode Enable (DBUART2)
//          <i> UART2 Rx FIFO timeout counter is stopped when the core is halted
//  <o2.27> UART3 Debug Mode Enable (DBUART3)
//          <i> UART3 Rx FIFO timeout counter is stopped when the core is halted
//  <o2.10> SPI0 Debug Mode Enable (DBSPI0)
//          <i> SPI0 Rx FIFO timeout counter is stopped when the core is halted
//  <o2.11> SPI1 Debug Mode Enable (DBSPI1)
//          <i> SPI1 Rx FIFO timeout counter is stopped when the core is halted
//  <o2.12> I2C0 Debug Mode Enable (DBI2C0)
//          <i> I2C0 timeout counter is stopped when the core is halted
//  <o2.13> I2C1 Debug Mode Enable (DBI2C1)
//          <i> I2C1 timeout counter is stopped when the core is halted
//  <o2.28> I2C2 Debug Mode Enable (DBI2C2)
//          <i> I2C2 timeout counter is stopped when the core is halted
//  <o2.15> SCI0 Debug Mode Enable (DBSCI0)
//          <i> SCI0 Waiting Time counter is stopped when the core is halted
//  <o2.21> SCI1 Debug Mode Enable (DBSCI1)
//          <i> SCI1 Waiting Time counter is stopped when the core is halted
//  <o2.16> BFTM0 Debug Mode Enable (DBBFTM0)
//          <i> BFTM0 Timer counter is stopped when the core is halted
//  <o2.17> BFTM1 Debug Mode Enable (DBBFTM1)
//          <i> BFTM1 Timer counter is stopped when the core is halted
//  <o2.22> SCTM0 Debug Mode Enable (DBSCTM0)
//          <i> SCTM0 Timer counter is stopped when the core is halted
//  <o2.23> SCTM1 Debug Mode Enable (DBSCTM1)
//          <i> SCTM1 Timer counter is stopped when the core is halted
//  <o2.24> SCTM2 Debug Mode Enable (DBSCTM2)
//          <i> SCTM2 Timer counter is stopped when the core is halted
//  <o2.25> SCTM3 Debug Mode Enable (DBSCTM3)
//          <i> SCTM3 Timer counter is stopped when the core is halted
//  <o2.30> PWM0 Debug Mode Enable (DBPWM0)
//          <i> PWM0 counter is stopped when the core is halted
//  <o2.31> PWM1 Debug Mode Enable (DBPWM1)
//          <i> PWM1 counter is stopped when the core is halted
//  </e>
  if (0)
  {
    _WDWORD(0x40088304, 0x00000000);
  }
}

DebugSupport();

/*----------------------------------------------------------------------------------------------------------*/
/* Uncomment to debug stack/heap underflow, overflow, and overwrite                                         */
/*----------------------------------------------------------------------------------------------------------*/
//BS Write __HT_check_sp, 2
//BS Write __HT_check_heap, 2

/*----------------------------------------------------------------------------------------------------------*/
/* Load debug symbol                                                                                        */
/*----------------------------------------------------------------------------------------------------------*/
//LOAD %L INCREMENTAL
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