21ic问答首页 - 新唐M481LGCAE 操作GPIO问题
新唐M481LGCAE 操作GPIO问题
第一次用新唐的MCU,如下程序的目的是设置GPIO的PA4引脚为高电平,但实际IO口无动作,由于用的基本是库函数,keil编译没报错,用DAPLink烧录也烧录成功verify OK
修改多次无果,求助论坛大佬们帮忙
#include <stdio.h>
#include "NuMicro.h"
#define PLL_CLOCK 192000000
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
//使能内部高速时钟12MHz
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
//等待内部高速时钟12MHz准备好
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
//开启PLL,设置PLL输出频率为192MHz
CLK_EnablePLL(CLK_PLLCTL_192MHz_HIRC, PLL_CLOCK);
//等待PLL时钟稳定
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
//HCLK分频器设置
CLK_SetHCLK( CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(0x4));
//设置M4核心系统时钟 = 1/2 HIRC 即6MHz
//CLK_SetSysTickClockSrc( CLK_CLKSEL0_STCLKSEL_HIRC_DIV2);
//设置APB0和APB1的分频系数,设置为2即192MHz二分频为96MHz
CLK->PCLKDIV = (CLK_PCLKDIV_APB0DIV_DIV2 | CLK_PCLKDIV_APB1DIV_DIV2);
//更新系统时钟
SystemCoreClockUpdate();
//清除PA4引脚的复用设置,即默认模式为GPIO
SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA4MFP_Msk);
SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA4MFP_GPIO);
//寄存器上锁保护
SYS_LockReg();
}
int main()
{
SYS_Init();
//设置PA4为输出模式
GPIO_SetMode( PA, BIT4, GPIO_MODE_OUTPUT);
//PA->MODE |= (GPIO_MODE_OUTPUT << (4*2));
//设置PA4为高电平
//PA4 = 1;
//PA->DOUT |= (1 << 4);
//PA->DOUT |= BIT4;
PA->DOUT = 0xFFFFFFFF;
/* Got no where to go, just loop forever */
while(1);
}
修改多次无果,求助论坛大佬们帮忙
#include <stdio.h>
#include "NuMicro.h"
#define PLL_CLOCK 192000000
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Unlock protected registers */
SYS_UnlockReg();
//使能内部高速时钟12MHz
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
//等待内部高速时钟12MHz准备好
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
//开启PLL,设置PLL输出频率为192MHz
CLK_EnablePLL(CLK_PLLCTL_192MHz_HIRC, PLL_CLOCK);
//等待PLL时钟稳定
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
//HCLK分频器设置
CLK_SetHCLK( CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(0x4));
//设置M4核心系统时钟 = 1/2 HIRC 即6MHz
//CLK_SetSysTickClockSrc( CLK_CLKSEL0_STCLKSEL_HIRC_DIV2);
//设置APB0和APB1的分频系数,设置为2即192MHz二分频为96MHz
CLK->PCLKDIV = (CLK_PCLKDIV_APB0DIV_DIV2 | CLK_PCLKDIV_APB1DIV_DIV2);
//更新系统时钟
SystemCoreClockUpdate();
//清除PA4引脚的复用设置,即默认模式为GPIO
SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA4MFP_Msk);
SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA4MFP_GPIO);
//寄存器上锁保护
SYS_LockReg();
}
int main()
{
SYS_Init();
//设置PA4为输出模式
GPIO_SetMode( PA, BIT4, GPIO_MODE_OUTPUT);
//PA->MODE |= (GPIO_MODE_OUTPUT << (4*2));
//设置PA4为高电平
//PA4 = 1;
//PA->DOUT |= (1 << 4);
//PA->DOUT |= BIT4;
PA->DOUT = 0xFFFFFFFF;
/* Got no where to go, just loop forever */
while(1);
}
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