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1. FIFO time-out interrupt occurs if the following conditions exist:<br />a. At least one character is in the FIFO.<br />b. The most recent serial character was received more than four continuous character times ago (if two stop bits are programmed, the second one is included in this time delay).<br />c. The most recent microprocessor read of the FIFO has occurred more than four continuous character times before. This causes a maximum character received command to interrupt an issued delay of 160ms at a 300 baud rate with a 12-bit character.<br /><br />＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊<br /><br />如要参考下文：<br />2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional to the baud rate).<br />3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads one character from the receiver FIFO.<br />4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received or after the microprocessor reads the receiver FIFO.<br /> |
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