我要写一个64K的正弦信号和32K的基带信号。 用的EPM240
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CH IS PORT(CLK,CLR:IN STD_LOGIC; D:OUT INTEGER RANGE 0 TO 255; BSOUT: OUT STD_LOGIC); END ENTITY CH; ARCHITECTURE ART OF CH IS COMPONENT SIN IS PORT(CLK,CLR:IN STD_LOGIC; D:OUT INTEGER RANGE 0 TO 255); END COMPONENT SIN; COMPONENT FP IS PORT(CLK:IN STD_LOGIC; CTRL1,CTRL2:OUT STD_LOGIC); END COMPONENT; COMPONENT BS IS PORT(CLK,CLR:IN STD_LOGIC; BSOUT:OUT STD_LOGIC); END COMPONENT; SIGNAL S1:STD_LOGIC; SIGNAL S2:STD_LOGIC; BEGIN U0: FP PORT MAP(CLK=>CLK,CTRL1=>S1,CTRL2=>S2); U1: SIN PORT MAP(CLK=>S1,CLR=>CLR,D=>D); U2: BS PORT MAP (CLK=>S2,CLR=>CLR,BSOUT=>BSOUT); END ARCHITECTURE ART; ------------------------分频64k、32k LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY FP IS PORT(CLK:IN STD_LOGIC; CTRL1,CTRL2:OUT STD_LOGIC); END; ARCHITECTURE ONE OF FP IS SIGNAL CLK1:STD_LOGIC; SIGNAL CLK2:STD_LOGIC; BEGIN PROCESS (CLK) VARIABLE CNT:INTEGER RANGE 0 TO 388; ----64K BEGIN IF CLK'event and CLK='1' THEN IF CNT=388 THEN CNT:=0; CLK1<=NOT CLK1; ELSE CNT:=CNT+1; END IF; END IF; END PROCESS; CTRL1<=CLK1; PROCESS (CLK) VARIABLE CNT:INTEGER RANGE 0 TO 776; ------32K BEGIN IF CLK'event and CLK='1' THEN IF CNT=776 THEN CNT:=0; CLK2<=NOT CLK2; ELSE CNT:=CNT+1; END IF; END IF; END PROCESS; CTRL2<=CLK2; END; ------------------------------sin library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity sin is port(clk,clr:in std_logic; d:out integer range 0 to 255); end entity; architecture behav of sin is begin process(clk,clr) variable tmp:integer range 0 to 63; begin if clr='0' then d<=0; elsif clk'event and clk='1' then if tmp=63 then tmp:=0; else tmp:=tmp+1; end if; case tmp is when 00=>d<=255; when 01=>d<=254; when 02=>d<=252; when 03=>d<=249; when 04=>d<=245; when 05=>d<=239; when 06=>d<=233; when 07=>d<=225; when 08=>d<=217; when 09=>d<=207; when 10=>d<=197; when 11=>d<=186; when 12=>d<=174; when 13=>d<=162; when 14=>d<=150; when 15=>d<=137; when 16=>d<=124; when 17=>d<=112; when 18=>d<=99; when 19=>d<=87; when 20=>d<=75; when 21=>d<=64; when 22=>d<=53; when 23=>d<=43; when 24=>d<=34; when 25=>d<=26; when 26=>d<=19; when 27=>d<=13; when 28=>d<=8; when 29=>d<=4; when 30=>d<=1; when 31=>d<=0; when 32=>d<=0; when 33=>d<=1; when 34=>d<=4; when 35=>d<=8; when 36=>d<=13; when 37=>d<=19; when 38=>d<=26; when 39=>d<=34; when 40=>d<=43; when 41=>d<=53; when 42=>d<=64; when 43=>d<=75; when 44=>d<=87; when 45=>d<=99; when 46=>d<=112; when 47=>d<=124; when 48=>d<=137; when 49=>d<=150; when 50=>d<=162; when 51=>d<=174; when 52=>d<=186; when 53=>d<=197; when 54=>d<=207; when 55=>d<=217; when 56=>d<=225; when 57=>d<=233; when 58=>d<=239; when 59=>d<=245; when 60=>d<=249; when 61=>d<=252; when 62=>d<=252; when 63=>d<=255; when others=>null; end case; end if; end process; end behav; ------------------------------BS library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity BS is port(clk,clr:in std_logic; bsout:out std_logic); end BS; architecture bhv of BS is signal ddout:std_logic_vector(3 downto 0); begin process(clk,clr) begin if clr='0' then ddout(3)<='1'; ddout(2 downto 0)<="000"; elsif clk'event and clk='1' then ddout(3)<=ddout(3)xor ddout(0); ddout(2)<=ddout(3); ddout(1)<=ddout(2); ddout(0)<=ddout(1); end if ; end process; bsout<=ddout(0); end bhv;
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