if key_ch_release = '1' then -- released => return to idle
release <= '1';
state <= ST_IDLE;
elsif cntr = REPEAT_START - 1 then -- timeout =>
cntr <= (others => '0');
press <= '1';
state <= ST_REPEAT;
end if;
这是用VHDL写的，但是这没有else，会产生latch吗？用Verilog怎么翻译过来,
还有other=>0,是所有输出都为０吗？？？？
Please answer!!!
Thanks thanks.
best regdards!
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