用CPLD采集图象时序 采用VHDL语言 (第一次VHDL写程) 程序如下: LIBRARY IEEE; USE IEEE.Std_Logic_1164.ALL; USE IEEE.Std_Logic_Arith.ALL; USE IEEE.Std_Logic_Unsigned.ALL;
entity SAA7111A is port ( -------SAA7111A_interface------------------------ LLC2 : in std_logic; HREF : in std_logic; VREF : in std_logic; HS : in std_logic; VS : in std_logic; RTS0 : in std_logic; VPO : in std_logic_vector(15 downto 0); TAKE : in std_logic; ------------------------------------------------- -------SRAM_interface---------------------------- addr : out std_logic_vector(18 downto 0); data : out std_logic_vector(15 downto 0); nCE : out std_logic; nWE : out std_logic; nOE : out std_logic; nUB : out std_logic; nLB : out std_logic; ------------------------------------------------- -------interrupt_line---------------------------- line : out std_logic ------------------------------------------------- ); end SAA7111A;
ARCHITECTURE SAA7111A_ac OF SAA7111A IS
SIGNAL TempAddr : STD_LOGIC_VECTOR(18 DOWNTO 0); SIGNAL couter : INTEGER range 0 TO 576; BEGIN couter <= 0; TempAddr <= "0000000000000000000"; addr <= "0000000000000000000"; A: PROCESS(LLC2) -------------sample,VREF
variable YUV422 : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN
IF LLC2'event AND LLC2='1' THEN YUV422 := VPO; IF VREF='1' AND HREF='1' AND TAKE='1' THEN data <= YUV422; addr <= TempAddr+1;
nCE <= '0'; nWE <= '0'; nOE <= '0'; nUB <= '0'; nLB <= '1'; ELSE nCE <= '1'; nWE <= '1'; nOE <= '1'; nUB <= '1'; nLB <= '1'; data <= "0000000000000000"; END IF; END IF; END PROCESS;
B:PROCESS(VREF) BEGIN IF VREF'event AND VREF='0' THEN IF RTS0='1' THEN TempAddr <= "0000000000000000000" ; line <= '1' ; END IF; END IF; END PROCESS;
END SAA7111A_ac;
编译的时候出现 Error:Line 35 signal"TempAddr"has multiple sources Error:Line 19 signal"addr"has multiple sources
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