我写了个Verilog简单程序，时钟信号输入是clk，输出：7个共阴极数码管段位seg（包括小数点共8段），7个位选择位是bit7。
程序思路：时钟信号送到8个10进制计数器计数，将前7位计数结果用数码管动态显示下来。完整程序如下：
module BCD7dp(seg,bit7,clk);
output [7:0]seg; //LED segment
output [6:0]bit7; //LED bit select
input clk;
reg [7:0]seg_rg;
wire [3:0]BD;
reg [6:0]bt_rg;
reg [2:0]cntl_rg;
wire [32:1]ctdat;
wire [8:1]tmp;
wire [2:0]cotl;
reg global_rst;
//下面是8个十进制计数器
ct4b U1(ctdat[4:1],tmp[1],global_rst,clk),
U2(ctdat[8:5],tmp[2],global_rst,tmp[1]),
U3(ctdat[12:9],tmp[3],global_rst,tmp[2]),
U4(ctdat[16:13],tmp[4],global_rst,tmp[3]),
U5(ctdat[20:17],tmp[5],global_rst,tmp[4]),
U6(ctdat[24:21],tmp[6],global_rst,tmp[5]),
U7(ctdat[28:25],tmp[7],global_rst,tmp[6]),
U8(ctdat[32:29],tmp[8],global_rst,tmp[7]);
//下面是4个8选1选择器，实际用7选1
MUX8sel U10(BD[3],{ctdat[8],ctdat[12],ctdat[16],ctdat[20],ctdat[24],ctdat[28],ctdat[32],ctdat[4]},cotl),
U11(BD[2],{ctdat[7],ctdat[11],ctdat[15],ctdat[19],ctdat[23],ctdat[27],ctdat[31],ctdat[3]},cotl),
U12(BD[1],{ctdat[6],ctdat[10],ctdat[14],ctdat[18],ctdat[22],ctdat[26],ctdat[30],ctdat[2]},cotl),
U13(BD[0],{ctdat[5],ctdat[9],ctdat[13],ctdat[17],ctdat[21],ctdat[25],ctdat[29],ctdat[1]},cotl);
always @(tmp[3]) //七段码译码器
begin
case(BD[3:0]) // hgfe_dcba
0:seg_rg=8'b0011_1111; // a
1:seg_rg=8'b0000_0110; //
2:seg_rg=8'b0101_1011; // f b
3:seg_rg=8'b0100_1111; //
4:seg_rg=8'b0110_0110; // g
5:seg_rg=8'b0110_1101; //
6:seg_rg=8'b0111_1101; // e c
7:seg_rg=8'b0000_0111; //
8:seg_rg=8'b0111_1111; // d h
9:seg_rg=8'b0110_0111; //common
default:seg_rg=8'bx; //
endcase
end
always @(tmp[6]) //七位计数
begin
cntl_rg=cntl_rg+1;
if(cntl_rg==7)
cntl_rg=0;
end
always @(tmp[6]) //7位要显示位的选择器
begin
case(cntl_rg[2:0])
0:bt_rg=7'b000_0001;
1:bt_rg=7'b000_0010;
2:bt_rg=7'b000_0100;
3:bt_rg=7'b000_1000;
4:bt_rg=7'b001_0000;
5:bt_rg=7'b010_0000;
6:bt_rg=7'b100_0000;
default:bt_rg=7'bx;
endcase
end
assign seg=seg_rg;
assign bit7=bt_rg;
assign global_rst=1;
endmodule
module MUX8sel(ot,I8,cnl3);
output ot;
reg ot;
input [0:7]I8;
input [0:2]cnl3;
always @(I8 or cnl3)
begin
case(cnl3)
0:ot=I8[0];
1:ot=I8[1];
2:ot=I8[2];
3:ot=I8[3];
4:ot=I8[4];
5:ot=I8[5];
6:ot=I8[6];
7:ot=I8[7];
endcase
end
endmodule
module ct4b(q,cout,global_rst,clk);
output [3:0]q;
output cout;
input global_rst;
input clk;
reg [3:0]q;
reg cout;
always @(global_rst)
begin
if(!global_rst)
begin
assign q=4'b0000;
assign cout=0;
end
else
begin
deassign q;
deassign cout;
end
end
always @(posedge clk)
begin
q = q+1;
if(q==4'b1010)
begin
q=4'b0000;
cout=1;
end
else
cout=0;
end
endmodule
可是用ISE9。1编译时出现如下错误：
Started : "Fit".
WARNING:Cpld - The signal(s) 'cntl_rg<0>' are in combinational feedback loops.
These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the hazard reduction circuitry.
Timing analysis of paths involving this node may be inaccurate or incomplete.
WARNING:Cpld - The signal(s) '_old_cntl_rg_1<1>' are in combinational feedback loops.
These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the hazard reduction circuitry.
Timing analysis of paths involving this node may be inaccurate or incomplete.
WARNING:Cpld - The signal(s) 'cntl_rg_cmp_eq0000' are in combinational feedback loops.
These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the hazard reduction circuitry.
Timing analysis of paths involving this node may be inaccurate or incomplete.
WARNING:Cpld - The signal(s) '_old_cntl_rg_1<2>' are in combinational feedback loops.
These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the hazard reduction circuitry.
Timing analysis of paths involving this node may be inaccurate or incomplete.
ERROR:Cpld:892 - Cannot place signal cntl_rg<0>. Consider reducing the
collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions.
.....
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options.
Process "Fit" failed
请问DX，程序到底有没有问题啊？变量cntl_rg有什么不妥的？将它改为wire也不行 |
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