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我写了个Verilog简单程序，时钟信号输入是clk，输出：7个共阴极数码管段位seg（包括小数点共8段），7个位选择位是bit7。<br />程序思路：时钟信号送到8个10进制计数器计数，将前7位计数结果用数码管动态显示下来。完整程序如下：<br />module BCD7dp(seg,bit7,clk);<br /> output [7:0]seg; //LED segment<br /> output [6:0]bit7; //LED bit select <br /> input clk;<br /> <br /> reg [7:0]seg_rg;<br /> wire [3:0]BD;<br /> reg [6:0]bt_rg;<br /> reg [2:0]cntl_rg;<br /> wire [32:1]ctdat;<br /> wire [8:1]tmp; <br /> wire [2:0]cotl;<br /> reg global_rst; <br /> //下面是8个十进制计数器<br /> ct4b U1(ctdat[4:1],tmp[1],global_rst,clk),<br /> U2(ctdat[8:5],tmp[2],global_rst,tmp[1]),<br /> U3(ctdat[12:9],tmp[3],global_rst,tmp[2]),<br /> U4(ctdat[16:13],tmp[4],global_rst,tmp[3]),<br /> U5(ctdat[20:17],tmp[5],global_rst,tmp[4]),<br /> U6(ctdat[24:21],tmp[6],global_rst,tmp[5]),<br /> U7(ctdat[28:25],tmp[7],global_rst,tmp[6]),<br /> U8(ctdat[32:29],tmp[8],global_rst,tmp[7]); <br /> //下面是4个8选1选择器，实际用7选1<br /> MUX8sel U10(BD[3],{ctdat[8],ctdat[12],ctdat[16],ctdat[20],ctdat[24],ctdat[28],ctdat[32],ctdat[4]},cotl),<br /> U11(BD[2],{ctdat[7],ctdat[11],ctdat[15],ctdat[19],ctdat[23],ctdat[27],ctdat[31],ctdat[3]},cotl),<br /> U12(BD[1],{ctdat[6],ctdat[10],ctdat[14],ctdat[18],ctdat[22],ctdat[26],ctdat[30],ctdat[2]},cotl),<br /> U13(BD[0],{ctdat[5],ctdat[9],ctdat[13],ctdat[17],ctdat[21],ctdat[25],ctdat[29],ctdat[1]},cotl);<br /> <br /> always @(tmp[3]) //七段码译码器<br /> begin<br /> case(BD[3:0]) // hgfe_dcba<br /> 0:seg_rg=8'b0011_1111; // a<br /> 1:seg_rg=8'b0000_0110; //<br /> 2:seg_rg=8'b0101_1011; // f b <br /> 3:seg_rg=8'b0100_1111; //<br /> 4:seg_rg=8'b0110_0110; // g<br /> 5:seg_rg=8'b0110_1101; //<br /> 6:seg_rg=8'b0111_1101; // e c <br /> 7:seg_rg=8'b0000_0111; //<br /> 8:seg_rg=8'b0111_1111; // d h<br /> 9:seg_rg=8'b0110_0111; //common <br /> default:seg_rg=8'bx; //<br /> endcase<br /> end <br /> <br /> always @(tmp[6]) //七位计数<br /> begin<br /> cntl_rg=cntl_rg+1;<br /> if(cntl_rg==7)<br /> cntl_rg=0; <br /> end<br /> <br /> always @(tmp[6]) //7位要显示位的选择器<br /> begin<br /> case(cntl_rg[2:0])<br /> 0:bt_rg=7'b000_0001;<br /> 1:bt_rg=7'b000_0010;<br /> 2:bt_rg=7'b000_0100;<br /> 3:bt_rg=7'b000_1000;<br /> 4:bt_rg=7'b001_0000;<br /> 5:bt_rg=7'b010_0000;<br /> 6:bt_rg=7'b100_0000;<br /> default:bt_rg=7'bx;<br /> endcase<br /> end <br /> <br /> assign seg=seg_rg;<br /> assign bit7=bt_rg;<br /> assign global_rst=1;<br />endmodule<br /><br />module MUX8sel(ot,I8,cnl3);<br /> output ot;<br /> reg ot;<br /> input [0:7]I8;<br /> input [0:2]cnl3;<br /><br /> always @(I8 or cnl3)<br /> begin <br /> case(cnl3)<br /> 0:ot=I8[0];<br /> 1:ot=I8[1];<br /> 2:ot=I8[2];<br /> 3:ot=I8[3];<br /> 4:ot=I8[4];<br /> 5:ot=I8[5];<br /> 6:ot=I8[6];<br /> 7:ot=I8[7];<br /> endcase <br /> end <br />endmodule<br /> <br />module ct4b(q,cout,global_rst,clk); <br /> output [3:0]q;<br /> output cout; <br /> input global_rst; <br /> input clk; <br /> <br /> reg [3:0]q; <br /> reg cout; <br /> <br /> always @(global_rst)<br /> begin <br /> if(!global_rst)<br /> begin<br /> assign q=4'b0000;<br /> assign cout=0;<br /> end<br /> else <br /> begin<br /> deassign q;<br /> deassign cout;<br /> end <br /> end<br /> <br /> always @(posedge clk)<br /> begin<br /> q = q+1;<br /> if(q==4'b1010)<br /> begin<br /> q=4'b0000;<br /> cout=1;<br /> end <br /> else <br /> cout=0;<br /> end <br />endmodule <br /><br />可是用ISE9。1编译时出现如下错误：<br />Started : "Fit".<br />WARNING:Cpld - The signal(s) 'cntl_rg<0>' are in combinational feedback loops.<br /> These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the hazard reduction circuitry.<br /> Timing analysis of paths involving this node may be inaccurate or incomplete.<br />WARNING:Cpld - The signal(s) '_old_cntl_rg_1<1>' are in combinational feedback loops.<br /> These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the hazard reduction circuitry.<br /> Timing analysis of paths involving this node may be inaccurate or incomplete.<br />WARNING:Cpld - The signal(s) 'cntl_rg_cmp_eq0000' are in combinational feedback loops.<br /> These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the hazard reduction circuitry.<br /> Timing analysis of paths involving this node may be inaccurate or incomplete.<br />WARNING:Cpld - The signal(s) '_old_cntl_rg_1<2>' are in combinational feedback loops.<br /> These signals may cause hazards/glitches. Apply the NOREDUCE parameter to the hazard reduction circuitry.<br /> Timing analysis of paths involving this node may be inaccurate or incomplete.<br /><br />ERROR:Cpld:892 - Cannot place signal cntl_rg<0>. Consider reducing the<br /> collapsing input limit or the product term limit to prevent the fitter from creating high input and/or high product term functions.<br />.....<br />ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with the selected implementation options.<br /><br />Process "Fit" failed<br />请问DX，程序到底有没有问题啊？变量cntl_rg有什么不妥的？将它改为wire也不行 |
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