8051扩展SRAM后，程序烤进去后没反应，不知道我们的工程哪儿错了，请版主指教！
我做了两个工程，好像都有问题，顶层文件如下，请版主帮我看看错在什么地方，万分感谢！
顶层文件１：
module USER_CORE8051 (p_reset, clk48m,p0o,p0i,p1o,p1i,p2o,rxd,txd,INT0,TCK,TDI,TDO,TMS,TRSTB,memdata,cs,wr,rd,ub,lb,adr);
parameter FMEMFILE = "flashmem.mem";
input p_reset;
input clk48m;
input TCK,TDI,TMS,TRSTB;
output TDO;
output[7:0] p0o,p1o,p2o;
input[7:0] p0i,p1i;
input INT0;
input rxd;
output txd;
inout [15:0] memdata;
output cs,wr,rd,ub,lb;
output [18:0] adr;
wire mcuclk,
nmcuclk,
clk18m;
wire dbgmempswr,mempsrd,memwr,memrd;
wire [7:0] memdatao;
wire [7:0] memdatai;
wire [15:0] memaddr;
wire [15:0] memdatao16;
wire [15:0] memdatai16;
wire[7:0] ramdatai;
wire[7:0] ramdatao;
wire[7:0] ramaddr;
wire ramwe;
wire ramoe;
wire n_reset;
wire[31:0] zeroes;
wire[31:0] ones;
wire GND_sig;
wire VCC_sig;
// Flash Memory signals
wire [17:0] fm_addr;
wire [31:0] fm_din;
wire [31:0] fm_dout;
wire [1:0] fm_byte_width;
wire fm_busy;
wire RESETN;
wire mempsacki_pre;
reg mempsacki;
assign fm_addr = {2'h0,memaddr[15:0]};
assign fm_byte_width = 2'b00;
assign fm_din = 32'b0;
assign GND_sig = 1'b0 ;
assign VCC_sig = 1'b1 ;
assign zeroes = {32{1'b0}} ;
assign ones = {32{1'b1}} ;
assign n_reset = ~p_reset;
assign memdatao16={memdatao,memdatao};
assign memdatai=mempsrd?fm_dout[7:0]:memdatai16[15:8];
assign memdatai16=memdata;
assign memdata=(dbgmempswr||memwr)?memdatao16:16'bzzzzzzzzzzzzzzzz;
assign adr={3'b000,memaddr};
assign wr=~(dbgmempswr||memwr);
assign rd=~(mempsrd||memrd);
assign cs=wr&rd;
assign ub=~(memwr||memrd);
assign lb=~(dbgmempswr||mempsrd);
assign mcuclk =clk18m;
assign nmcuclk = ~mcuclk ;
assign GND0 = 1'b0;
assign VCC1 = 1'b1;
pll33m pll33m(
.POWERDOWN(VCC_sig),
.CLKA(clk48m),
.GLA(clk18m)
);
CORE8051 CORE8051_inst (.nreset(n_reset), .clk(mcuclk), .clkcpu(mcuclk),
.clkper(mcuclk), .port0i(p0i),
.port1i(p1i), .port2i(zeroes[7:0]), .port3i(zeroes[7:0]),
.int0(INT0), .int1(VCC_sig), .int0a(GND_sig), .int1a(GND_sig),
.int2(GND_sig), .int3(GND_sig), .int4(GND_sig), .int5(GND_sig),
.int6(GND_sig), .int7(GND_sig), .rxd0i(rxd), .t0(GND_sig),.t1(GND_sig),
.nrsto(RESETN), .nrsto_nc(), .clkcpu_en(), .clkper_en(), .movx(), .port0o(p0o),
.port1o(p1o), .port2o(p2o), .port3o(), .rxd0o(), .txd0(txd), .mempsacki(mempsacki),
.memacki(VCC_sig), .memdatai(memdatai), .mempsacko(), .memdatao(memdatao),
.memaddr(memaddr), .mempsrd(mempsrd), .memwr(memwr), .memrd(memrd), .ramdatai(ramdatai),
.ramdatao(ramdatao), .ramaddr(ramaddr), .ramwe(ramwe), .ramoe(ramoe),
.sfrdatai(zeroes[7:0]), .sfrdatao(), .sfraddr(), .sfrwe(), .sfroe(),
.TCK(TCK), .TMS(TMS), .TDI(TDI), .TDO(TDO), .TRSTB(TRSTB),
.BreakIn(GND_sig), .BreakOut(), .membank(zeroes[3:0]), .dbgmempswr(dbgmempswr),
.TrigOut(), .AuxOut(), .TraceA(), .TraceDI(), .TraceDO(zeroes[19:0]),
.TraceWr());
RAM256X8 internal_RAM(
.WD(ramdatao),
.RD(ramdatai),
.WEN(ramwe),
.REN(ramoe),
.WADDR(ramaddr),
.RADDR(ramaddr),
.WCLK(mcuclk),
.RCLK(nmcuclk)
);
NVM #(.MEMORYFILE(FMEMFILE)) u_FLASH_MEM (
.ADDR(fm_addr),
.WD(fm_din),
.DATAWIDTH(fm_byte_width),
.REN(VCC1),
.READNEXT(GND0),
.PAGESTATUS(GND0),
.WEN(GND0),
.ERASEPAGE(GND0),
.PROGRAM(GND0),
.SPAREPAGE(GND0),
.AUXBLOCK(GND0),
.UNPROTECTPAGE(GND0),
.OVERWRITEPAGE(GND0),
.DISCARDPAGE(GND0),
.OVERWRITEPROTECT(GND0),
.PAGELOSSPROTECT(GND0),
.PIPE(VCC1),
.LOCKREQUEST(VCC1),
.CLK(fasterclk),
.RESET(RESETN),
.RD(fm_dout),
.BUSY(fm_busy),
.STATUS()
);
always @(negedge mcuclk or negedge RESETN)
begin
if (!RESETN)
mempsacki <= 1'b0;
else
mempsacki <= mempsacki_pre;
end
assign mempsacki_pre = ~fm_busy;
endmodule
顶层文件２：
//8051模块
module USER_CORE8051 (reset, clk48m,p0o,p0i,p1o,p1i,p2o,p2i,p3o,p3i,rxd,txd,INT0,INT1,TCK,TDI,TDO,TMS,TRSTB,memdata,cs,wr,rd,ub,lb,adr);
input reset;
input clk48m;
output[7:0] p0o,p1o,p2o,p3o; //51单片机的P1,P2,P3 输出口
input[7:0] p0i,p1i,p2i,p3i; //51单片机的P1,P2输入口
input INT0,INT1; //单片机中断信号
input rxd; //51单片机串口接收数据端口
output txd; //51单片机串口发送数据端口
input TCK,TDI,TMS,TRSTB;
output TDO;
inout [15:0] memdata;
output cs,wr,rd,ub,lb;
output [18:0] adr;
wire mcuclk,
nmcuclk;
wire dbgmempswr,mempsrd,memwr,memrd;
wire [7:0] memdatao;
wire [7:0] memdatai;
wire [15:0] memaddr;
wire [15:0] memdatao16;
wire [15:0] memdatai16;
wire[7:0] ramdatai;
wire[7:0] ramdatao;
wire[7:0] ramaddr;
wire mempsacki;
wire ramwe;
wire ramoe;
wire n_reset;
wire[31:0] zeroes;
wire[31:0] ones;
wire GND_sig;
wire VCC_sig;
// Flash Memory signals
wire [17:0] fm_addr;
wire [31:0] fm_din;
wire [31:0] fm_dout;
wire [1:0] fm_byte_width;
wire fm_busy;
wire mempsacki_pre;
wire RESETN;
assign fm_addr = {2'h0,memaddr[15:0]};
assign fm_din = 32'b0;
assign GND_sig = 1'b0 ;
assign VCC_sig = 1'b1 ;
assign zeroes = {32{1'b0}} ;
assign ones = {32{1'b1}} ;
assign n_reset = ~reset; //低电平复位
assign memdatao16={memdatao,memdatao};
assign memdatai=mempsrd?fm_dout[7:0]:memdatai16[15:8];
assign memdatai16=memdata;
assign memdata=(dbgmempswr||memwr)?memdatao16:16'bzzzzzzzzzzzzzzzz;
assign adr={3'b000,memaddr};
assign wr=~(dbgmempswr||memwr);
assign rd=~(mempsrd||memrd);
assign cs=wr&rd;
assign ub=~(memwr||memrd);
assign lb=~(dbgmempswr||mempsrd);
assign nmcuclk = ~mcuclk ;
/*Flsahmemory作为8051的内部ROM*/
flashmem U1(
.USER_CLK(!mcuclk),
.USER_RESET(RESETN),
.USER_ADD(fm_addr),
.USER_READ(mempsrd),
.USER_WIDTH(2'b00),
.USER_DOUT(fm_dout), //数据位宽为8位
.USER_READ_NEXT(1'b0), //正常读写
.USER_NVM_BUSY(fm_busy)
);
/*Flsahmemory读控制模块*/
Core8051_ROM_Ctr U2(
.clk_ctr(mcuclk),
.rst(!RESETN),
.BUSY(fm_busy),
.mempsacki(mempsacki)
);
//例化PLL
pll33m pll33m(
.POWERDOWN(VCC_sig),
.CLKA(clk48m),
.GLA(mcuclk)
);
//例化8051模块
CORE8051 CORE8051_inst (.nreset(n_reset), .clk(mcuclk), .clkcpu(mcuclk),
.clkper(mcuclk), .port0i(p0i),
.port1i(p1i), .port2i(p2i), .port3i(p3i),
.int0(INT0), .int1(INT1), .int0a(GND_sig), .int1a(GND_sig),
.int2(GND_sig), .int3(GND_sig), .int4(GND_sig), .int5(GND_sig),
.int6(GND_sig), .int7(GND_sig), .rxd0i(rxd), .t0(GND_sig),.t1(GND_sig),
.nrsto(RESETN), .nrsto_nc(), .clkcpu_en(), .clkper_en(), .movx(), .port0o(p0o),
.port1o(p1o), .port2o(p2o), .port3o(p3o), .rxd0o(), .txd0(txd), .mempsacki(mempsacki),
.memacki(VCC_sig), .memdatai(memdatai), .mempsacko(), .memdatao(memdatao),
.memaddr(memaddr), .mempsrd(mempsrd), .memwr(memwr), .memrd(memrd), .ramdatai(ramdatai),
.ramdatao(ramdatao), .ramaddr(ramaddr), .ramwe(ramwe), .ramoe(ramoe),
.sfrdatai(zeroes[7:0]), .sfrdatao(), .sfraddr(), .sfrwe(), .sfroe(),
.TCK(TCK), .TMS(TMS), .TDI(TDI), .TDO(TDO), .TRSTB(TRSTB),
.BreakIn(GND_sig), .BreakOut(), .membank(zeroes[3:0]), .dbgmempswr(),
.TrigOut(), .AuxOut(), .TraceA(), .TraceDI(), .TraceDO(zeroes[19:0]),
.TraceWr());
//例化单片机RAM模块
RAM256X8 internal_RAM(
.WD(ramdatao),
.RD(ramdatai),
.WEN(ramwe),
.REN(ramoe),
.WADDR(ramaddr),
.RADDR(ramaddr),
.WCLK(mcuclk),
.RCLK(nmcuclk)
);
endmodule
谢谢版主！
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