`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:46:31 03/20/07
// Design Name:
// Module Name: inout_module
// Project Name:
// Target Device:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module inout_module(
clk_125,
rst_n,
s,
cl,
d_out,
d_in,
mult_out0,
mult_out1,
mult_out2,
mult_out3,
mult_out4,
mult_out5,
mult_out6,
mult_out7,
mult_out8,
mult_out9,
mult_out10,
mult_out11,
mult_out12,
mult_out13,
mult_out14,
mult_out15
);
input clk_125,rst_n,s,cl;
input [7:0] d_in;
input [7:0] mult_out0;
input [7:0] mult_out1;
input [7:0] mult_out2;
input [7:0] mult_out3;
input [7:0] mult_out4;
input [7:0] mult_out5;
input [7:0] mult_out6;
input [7:0] mult_out7;
input [7:0] mult_out8;
input [7:0] mult_out9;
input [7:0] mult_out10;
input [7:0] mult_out11;
input [7:0] mult_out12;
input [7:0] mult_out13;
input [7:0] mult_out14;
input [7:0] mult_out15;
output [7:0] d_out;
reg [7:0] d_out;
reg [4:0] cont;
reg [7:0] dout;
always@(posedge clk_125 or negedge rst_n)begin
if(!rst_n)
begin
cont <= 0;
d_out <= 8'b0;
dout <= 8'b0;
end
else
begin
if(~s)
begin
d_out <= d_in;
end
else if(s)
begin
cont <= cont + 1;
d_out <= dout;
end
else if(cl)
begin
d_out <= 8'b0;
dout <= 0;
cont <= 0;
end
end
end
/*always@(posedge clk_125 or negedge rst_n)
begin
if(!rst_n)
cont <= 0;
else
begin
if(s)
cont <= cont +1;
else if(cl)
cont <= 0;
end
end */
always@(cont or mult_out0 or mult_out1 or mult_out2 or mult_out3 or mult_out4 or mult_out5 or mult_out6 or mult_out7 or mult_out8 or mult_out9 or mult_out10 or mult_11 or mult_out12 or mult_out13 or mult_out14 or mult_15)
case(cont)
5'b00001: dout = mult_out15;
5'b00010: dout = mult_out14;
5'b00011: dout = mult_out13;
5'b00100: dout = mult_out12;
line119 5'b00101: dout = mult_out11;
5'b00110: dout = mult_out10;
5'b00111: dout = mult_out9;
5'b01000: dout = mult_out8;
5'b01001: dout = mult_out7;
5'b01010: dout = mult_out6;
5'b01011: dout = mult_out5;
5'b01100: dout = mult_out4;
5'b01101: dout = mult_out3;
5'b01110: dout = mult_out2;
5'b01111: dout = mult_out1;
default : dout = mult_out0;
endcase
endmodule
综合时报错如下：
ERROR:HDLCompilers:26 - "inout_module.v" line 119 expecting 'endcase', found '\241'
ERROR:HDLCompilers:26 - "inout_module.v" line 119 expecting 'endmodule', found '5'
ERROR: XST failed
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