verilog编程风格与优化

只看该作者 · 2008-7-21 13:13

sample1:
引用:
always @(ilut_index[7:0])
begin
if(ilut_index[7]) begin
      ron = 1;
  end
else if(ilut_index[6]) begin
     ron = 1;
end
else if(ilut_index[5]) begin
     ron = 1;
end
else if(ilut_index[4]) begin
     ron = 1;
end
else if(ilut_index[3]) begin
     ron = 1;
end
else if(ilut_index[2]) begin
     ron = 1;
end
else if(ilut_index[1]) begin
     ron = 1;
end
else begin
     ron = 0;
end
end
sample2:
引用:
always @(ilut_index[7:0])
begin
if(ilut_index[7] == 1'b1) begin
      ron = 1;
  end
else if(ilut_index[7:6] == 2'b01) begin
     ron = 1;
end
else if(ilut_index[7:5] == 3'b001) begin
     ron = 1;
end
else if(ilut_index[7:4] == 4'b0001) begin
     ron = 1;
end
else if(ilut_index[7:3] == 5'b00001) begin
     ron = 1;
end
else if(ilut_index[7:2] == 6'b000001) begin
     ron = 1;
end
else if(ilut_index[7:1] == 7'b0000001) begin
     ron = 1;
end
else begin
     ron = 0;
end
end
sample3:
引用:
always @(ilut_index[7:0])
begin
if(ilut_index[7] == 1'b1) begin
      ron = 1;
  end
if(ilut_index[7:6] == 2'b01) begin
     ron = 1;
end
if(ilut_index[7:5] == 3'b001) begin
     ron = 1;
end
if(ilut_index[7:4] == 4'b0001) begin
     ron = 1;
end
if(ilut_index[7:3] == 5'b00001) begin
     ron = 1;
end
if(ilut_index[7:2] == 6'b000001) begin
     ron = 1;
end
if(ilut_index[7:1] == 7'b0000001) begin
     ron = 1;
end
else begin
     ron = 0;
end
end

sample4:
always @(ilut_index[7:0])
begin
if((ilut_index[7] == 1'b1)         ||
   (ilut_index[7:6] == 2'b01)      ||
   (ilut_index[7:5] == 3'b001)     ||
   (ilut_index[7:4] == 3'b0001)    ||
   (ilut_index[7:3] == 3'b00001)   ||
   (ilut_index[7:2] == 3'b000001)  ||
   (ilut_index[7:1] == 3'b0000001) begin
      ron = 1;
  end
  else begin
     ron = 0;
  end
  end
sample5:
引用:
always @(ilut_index[7:0])
begin
casex (ilut_index[7:0])
8'b1xxx_xxxx : ron = 1;
8'b01xx_xxxx : ron = 1;
8'b001x_xxxx : ron = 1;
8'b0001_xxxx : ron = 1;
8'b0000_1xxx : ron = 1;
8'b0000_01xx : ron = 1;
8'b0000_001x : ron = 1;
default : ron = 0;
endcase
end
sample6:
引用:
always @(ilut_index[7:0])
begin
casex (ilut_index[7:0])
8'b1xxx_xxxx ,
8'b01xx_xxxx ,
8'b001x_xxxx ,
8'b0001_xxxx ,
8'b0000_1xxx ,
8'b0000_01xx ,
8'b0000_001x : begin
   ron = 1;
end
default: ron = 0;
endcase
end
上面代码等效
问题：
  1.请问上面几种风格优略如何？
  2.从综合角度，速度及门数方面有没区别，请作一比较？