原程序如下：library ieee;
use ieee.std_logic_1164.all; -- we use IEEE standard 1164 logic types.
use ieee.numeric_std.all; -- + and - operators
entity encoder is ----------------------------ENTITY---------------------
port(
clk : in std_logic; -- everything clocks on rising edge
rst : in std_logic; -- reset--'1'=clean
datain : in std_logic_vector(7 downto 0); -- data bus
---------
Kin : in std_logic; -- 特殊字符kin为1时正常编码，0时为特殊码值。
--------------------------------------------------------------
dataout : out std_logic_vector(9 downto 0);
frameout :out std_logic
-- invalid_k : out std_logic--输入特殊字符时共有12个（0-11),其余均为无效值
);
end encoder;
architecture empty of encoder is -------- ARCHITECTURE empty --------
signal data_in : std_logic_vector(7 downto 0);
signal data6b : std_logic_vector(6 downto 0);--默认游程值为0下的5位转六位编码,第0位显示译码后码值是否平衡，0为平衡，1为不平衡。
signal data4b : std_logic_vector(4 downto 0);--默认游程值为0下的3位转4位编码,第0位显示译码后码值是否平衡，0为平衡，1为不平衡。
signal data_out : std_logic_vector(9 downto 0);
signal rd_initial: std_logic :='0';--初始游程值
signal rd_3b: std_logic; --译码8位数据后的游程值，用于下个8位译码
signal rd_end: std_logic :='0';
begin
process(kin,datain)
begin
data_in<=datain;
case data_in(7 downto 5)is--3b/4b when rd_initial=0;
when "000"=> data4b<="01001";
when "001"=> data4b<="10010";
when "010"=> data4b<="01010";
when "011"=> data4b<="00110";
when "100"=> data4b<="00101";
when "101"=> data4b<="10100";
when "110"=> data4b<="01100";
when "111"=> if(kin='0')then
data4b<="10001";
else data4b<="00011";
end if;
end case;
case data_in(4 downto 0) is--5b/1b when rd_initial=0;
when "00000"=> data6b<="0110001";
when "00001"=> data6b<="1000101";
when "00010"=> data6b<="0100101";
when "00011"=> data6b<="1100010";
when "00100"=> data6b<="0010101";
when "00101"=> data6b<="1010010";
when "00110"=> data6b<="0110010";
when "00111"=> data6b<="0001111";
when "01000"=> data6b<="0001101";
when "01001"=> data6b<="1001010";
when "01010"=> data6b<="0101010";
when "01011"=> data6b<="1101000";
when "01100"=> data6b<="0011010";
when "01101"=> data6b<="1011000";
when "01110"=> data6b<="0111000";
when "01111"=> data6b<="0101110";
when "10000"=> data6b<="1001001";
when "10001"=> data6b<="1000110";
when "10010"=> data6b<="0100110";
when "10011"=> data6b<="0011010";
when "10100"=> data6b<="0010110";
when "10101"=> data6b<="1010100";
when "10110"=> data6b<="0110100";
when "10111"=> data6b<="0001011";
when "11000"=> data6b<="0011001";
when "11001"=> data6b<="1001100";
when "11010"=> data6b<="0101100";
when "11011"=> data6b<="0010011";
when "11100"=> data6b<="0011100";
when "11101"=> data6b<="0100011";
when "11110"=> data6b<="1000011";
when "11111"=> data6b<="0101001";
end case;
--if ((kin='0')and((data_in/="00011100")or(data_in/="00111100")or(data_in/="01011100")or(data_in/="01111100")or(data_in/="10011100")or(data_in/="10111100")or(data_in/="11011100")or(data_in/="11111100")or(data_in/="11110111")or(data_in/="11111011")
--or(data_in/="11111101")or(data_in/="11111110")))
-- then invalid_k<='1';
--else invalid_k<='0';
-- end if;
end process;
process(clk,rst)
begin
if(rst='1')then
rd_initial='0';
frameout<='0';
else
if(clk'event and clk='1')then
if(rd_initial='0')then
dataout(9 downto 4)<=data6b(6 downto 1);
else if(rd_initial='1'and data6b(0)='1')then-----------------
dataout(9 downto 4)<=not(data6b(6 downto 1));
elsif(rd_initial='1'and data6b(0)='0')then
dataout(9 downto 4)<=data6b(6 downto 1);
end if;
end if;
if(rd_3b='0')then
dataout(3 downto 0)<=data4b(4 downto 1);
else if (rd_3b='1'and data4b(0)='1')
then
dataout(3 downto 0)<=not(data4b(4 downto 1));
elsif(rd_3b='1'and data4b(0)='0')then
dataout(3 downto 0)<=data4b(4 downto 1);
end if;
end if;
frameout<='1';
rd_initial<=rd_end;
end if;
end if;
end process;
rd_3b<=(rd_initial) xor(data6b(0));
rd_end<=(rd_3b) xor (data4b(0));
end empty;
现对其修改，加入count使其24个时钟解一次码仿真后却无结果，求帮忙。
修改后程序如下：library ieee;
use ieee.std_logic_1164.all; -- we use IEEE standard 1164 logic types.
use ieee.numeric_std.all; -- + and - operators
entity encoder is ----------------------------ENTITY---------------------
port(
clk : in std_logic; -- everything clocks on rising edge
rst : in std_logic; -- reset--'1'=clean
datain : in std_logic_vector(7 downto 0); -- data bus
---------
Kin : in std_logic; -- 特殊字符kin为1时正常编码，0时为特殊码值。
--------------------------------------------------------------
dataout : out std_logic_vector(9 downto 0);
frameout :out std_logic
-- invalid_k : out std_logic--输入特殊字符时共有12个（0-11),其余均为无效值
);
end encoder;
architecture empty of encoder is -------- ARCHITECTURE empty --------
signal data_in : std_logic_vector(7 downto 0);
signal data6b : std_logic_vector(6 downto 0);--默认游程值为0下的5位转六位编码,第0位显示译码后码值是否平衡，0为平衡，1为不平衡。
signal data4b : std_logic_vector(4 downto 0);--默认游程值为0下的3位转4位编码,第0位显示译码后码值是否平衡，0为平衡，1为不平衡。
signal data_out : std_logic_vector(9 downto 0);
signal rd_initial: std_logic :='0';--初始游程值
signal rd_3b : std_logic; --译码8位数据后的游程值，用于下个8位译码
signal rd_end :std_logic :='0';
SIGNAL count :INTEGER RANGE 0 TO 2000;
begin
PROCESS(clk,rst)
BEGIN
if(rst='1')then --dataout<="0000000000";
--frameout<='0';
count<=0;
elsif (clk'EVENT AND clk='1') THEN
IF(count=24) THEN
count<=0;
ELSE
count<=count+1;
END IF;
END IF;
END PROCESS;
process(kin,count,datain)
begin
if(count=1)then
data_in<=datain;
case data_in(7 downto 5)is--3b/4b when rd_initial=0;
when "000"=> data4b<="01001";
when "001"=> data4b<="10010";
when "010"=> data4b<="01010";
when "011"=> data4b<="00110";
when "100"=> data4b<="00101";
when "101"=> data4b<="10100";
when "110"=> data4b<="01100";
when "111"=> if(kin='0')then
data4b<="10001";
else data4b<="00011";
end if;
end case;
case data_in(4 downto 0) is--5b/1b when rd_initial=0;
when "00000"=> data6b<="0110001";
when "00001"=> data6b<="1000101";
when "00010"=> data6b<="0100101";
when "00011"=> data6b<="1100010";
when "00100"=> data6b<="0010101";
when "00101"=> data6b<="1010010";
when "00110"=> data6b<="0110010";
when "00111"=> data6b<="0001111";
when "01000"=> data6b<="0001101";
when "01001"=> data6b<="1001010";
when "01010"=> data6b<="0101010";
when "01011"=> data6b<="1101000";
when "01100"=> data6b<="0011010";
when "01101"=> data6b<="1011000";
when "01110"=> data6b<="0111000";
when "01111"=> data6b<="0101110";
when "10000"=> data6b<="1001001";
when "10001"=> data6b<="1000110";
when "10010"=> data6b<="0100110";
when "10011"=> data6b<="0011010";
when "10100"=> data6b<="0010110";
when "10101"=> data6b<="1010100";
when "10110"=> data6b<="0110100";
when "10111"=> data6b<="0001011";
when "11000"=> data6b<="0011001";
when "11001"=> data6b<="1001100";
when "11010"=> data6b<="0101100";
when "11011"=> data6b<="0010011";
when "11100"=> data6b<="0011100";
when "11101"=> data6b<="0100011";
when "11110"=> data6b<="1000011";
when "11111"=> data6b<="0101001";
end case;
--if ((kin='0')and((data_in/="00011100")or(data_in/="00111100")or(data_in/="01011100")or(data_in/="01111100")or(data_in/="10011100")or(data_in/="10111100")or(data_in/="11011100")or(data_in/="11111100")or(data_in/="11110111")or(data_in/="11111011")
--or(data_in/="11111101")or(data_in/="11111110")))
-- then invalid_k<='1';
--else invalid_k<='0';
end if;
if(count=0)then
-- rd_initial<='0';
frameout<='0';
dataout<="0000000000";
else
if(count=2)then
if(rd_initial='0')then
dataout(9 downto 4)<=data6b(6 downto 1);
else if(rd_initial='1'and data6b(0)='1')then-----------------
dataout(9 downto 4)<=not(data6b(6 downto 1));
elsif(rd_initial='1'and data6b(0)='0')then
dataout(9 downto 4)<=data6b(6 downto 1);
end if;
end if;
if(rd_3b='0')then
dataout(3 downto 0)<=data4b(4 downto 1);
else if (rd_3b='1'and data4b(0)='1')
then
dataout(3 downto 0)<=not(data4b(4 downto 1));
elsif(rd_3b='1'and data4b(0)='0')then
dataout(3 downto 0)<=data4b(4 downto 1);
end if;
end if;
frameout<='1';
rd_initial<=rd_end;
-- dataout<=data_out;
end if;
end if;
end process;
rd_3b<=(rd_initial) xor(data6b(0));
rd_end<=(rd_3b) xor (data4b(0));
end empty; |
楼主
标题置顶
标题高亮
