用altera的EPM7128做地址译码和IO扩展，代码如下：
`define IOCADDR 9'h1f8 // IO_C地址, (0x1F800-0x1F8FF), input
`define IOFADDR 9'h1f9 // IO_F地址, (0x1F900-0x1F9FF), input
`define IOAADDR 9'h1fa // IO_A地址, (0x1FA00-0x1FAFF), output
`define IOBADDR 9'h1fb // IO_B地址, (0x1FB00-0x1FBFF), output
`define IODADDR 9'h1fc // IO_D地址, (0x1FC00-0x1FCFF), output
`define IOEADDR 9'h1fd // IO_E地址, (0x1FD00-0x1FDFF), output
`define CSRAM 9'h1f8 // 外部扩展RAM选通信号, 126k空间 (0x00000-0x1F7FF)
module Main (lowAddrData, highAddr, lowAddr, ale, wr, rd,
csRAM, ioaVector, iobVector, iocVector,
iodVector, ioeVector, iofVector) ;
inout [7:0] lowAddrData ;
input [16:8] highAddr ;
input ale, wr, rd ;
output [7:0] lowAddr = 8'hff ;
output csRAM = 'b1 ;
output [7:0] ioaVector = 8'hff ;
output [7:0] iobVector = 8'hff ;
input [7:0] iocVector ;
output [7:0] iodVector = 8'hff ;
output [7:0] ioeVector = 8'hff ;
input [7:0] iofVector ;
wire [7:0] lowAddrData ;
reg [7:0] lowAddrData_Input ;
reg csRAM ;
reg [7:0] lowAddr ;
reg [7:0] ioaVector ;
reg [7:0] iobVector ;
wire [7:0] iocVector ;
reg [7:0] iodVector ;
reg [7:0] ioeVector ;
wire [7:0] iofVector ;
always // 锁存低8位地址
@ (negedge ale)
begin
lowAddr = lowAddrData ;
end
always // 地址译码，RAM CS为低电平
@ (ale or highAddr) // 电平触发
begin
if ( ale == 1 )
csRAM = 'b1 ;
else
if ( highAddr < `CSRAM )
csRAM = 'b0 ;
else
csRAM = 'b1 ;
end
always // 写数据
@ (negedge wr) // 下降沿触发
begin
if ( highAddr >= `IOEADDR )
ioeVector[7:0] = lowAddrData[7:0] ;
else if ( highAddr >= `IODADDR )
iodVector[7:0] = lowAddrData[7:0] ;
else if ( highAddr >= `IOBADDR )
iobVector[7:0] = lowAddrData[7:0] ;
else if ( highAddr >= `IOAADDR )
ioaVector[7:0] = lowAddrData[7:0] ;
end
assign lowAddrData[7:0] = lowAddrData_Input[7:0] ;
always // read data
@ (negedge rd) // negedge trig
begin
if ( highAddr >= `IOFADDR )
lowAddrData_Input[7:0] = iofVector[7:0] ;
else if ( highAddr >= `IOCADDR )
lowAddrData_Input[7:0] = iocVector[7:0] ;
end
endmodule
用quartus 5.0时正常，但在quartus 7.1中出现很多警告，大家看看有没有问题？
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