typedef struct UART_MemMap {
uint8_t BDH; /*!< UART Baud Rate Registers:High, offset: 0x0 */
uint8_t BDL; /*!< UART Baud Rate Registers: Low, offset: 0x1 */
uint8_t C1; /*!< UART Control Register 1, offset: 0x2 */
uint8_t C2; /*!< UART Control Register 2, offset: 0x3 */
uint8_t S1; /*!< UART Status Register 1, offset: 0x4 */
uint8_t S2; /*!< UART Status Register 2, offset: 0x5 */
uint8_t C3; /*!< UART Control Register 3, offset: 0x6 */
uint8_t D; /*!< UART Data Register, offset: 0x7 */
uint8_t MA1; /*!< UART Match Address Registers 1, offset: 0x8 */
uint8_t MA2; /*!< UART Match Address Registers 2, offset: 0x9 */
uint8_t C4; /*!< UART Control Register 4, offset: 0xA */
uint8_t C5; /*!< UART Control Register 5, offset: 0xB */
uint8_t ED; /*!< UART Extended Data Register, offset: 0xC */
uint8_t MODEM; /*!< UART Modem Register, offset: 0xD */
uint8_t IR; /*!< UART Infrared Register, offset: 0xE */
uint8_t RESERVED_0[1];
uint8_t PFIFO; /*!< UART FIFO Parameters, offset: 0x10 */
uint8_t CFIFO; /*!< UART FIFO Control Register, offset: 0x11 */
uint8_t SFIFO; /*!< UART FIFO Status Register, offset: 0x12 */
uint8_t TWFIFO; /*!< UART FIFO Transmit Watermark, offset: 0x13 */
uint8_t TCFIFO; /*!< UART FIFO Transmit Count, offset: 0x14 */
uint8_t RWFIFO; /*!< UART FIFO Receive Watermark, offset: 0x15 */
uint8_t RCFIFO; /*!< UART FIFO Receive Count, offset: 0x16 */
uint8_t RESERVED_1[1];
uint8_t C7816; /*!< UART 7816 Control Register, offset: 0x18 */
uint8_t IE7816; /*!< UART 7816 Interrupt Enable Register, offset: 0x19 */
uint8_t IS7816; /*!< UART 7816 Interrupt Status Register, offset: 0x1A */
union { /* offset: 0x1B */
uint8_t WP7816_T_TYPE0; /*!< UART 7816 Wait Parameter Register, offset: 0x1B */
uint8_t WP7816_T_TYPE1; /*!< UART 7816 Wait Parameter Register, offset: 0x1B */
};
uint8_t WN7816; /*!< UART 7816 Wait N Register, offset: 0x1C */
uint8_t WF7816; /*!< UART 7816 Wait FD Register, offset: 0x1D */
uint8_t ET7816; /*!< UART 7816 Error Threshold Register, offset: 0x1E */
uint8_t TL7816; /*!< UART 7816 Transmit Length Register, offset: 0x1F */
} volatile *UART_MemMapPtr; |