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/********************************************************
* Tilte: EM78P153S include file *
* Description: The Definition of EM78P153S Registers *
* Author: WQL *
* Date: 6/9/2009 *
* Version: v1.0 *
********************************************************/
/**************Operational Registers Define*************/
/************************R0~R2F*************************/
static unsigned int IAR @0x00:rpage 0;
static unsigned int TCC @0x01:rpage 0;
static unsigned int PC @0x02:rpage 0;
static unsigned int STATUS @0x03:rpage 0;
static unsigned int RSR @0x04:rpage 0;
static unsigned int PORT5 @0x05:rpage 0;
static unsigned int PORT6 @0x06:rpage 0;
static unsigned int ISR @0x0F:rpage 0;
/* STATUS bits */
static bit RST @0x03@7:rpage 0;//Bit Of Reset Type
static bit GP1 @0x03@6:rpage 0;
static bit GP0 @0x03@5:rpage 0;//general purpose read/write bits
static bit T @0x03@4:rpage 0;//time-out bit
static bit P @0x03@3:rpage 0;//power down bit
static bit Z @0x03@2:rpage 0;//Zero flag
static bit DC @0x03@1:rpage 0;//Auxiliary carry bit
static bit C @0x03@0:rpage 0;//carry flag
/* R4 bits */
// Bits 5~0 are used to select registers(address: 00~06,0F~2F)
// in the indirect addressing mode
// Bits 7~6 are general-purpose read/write bits
/* R5 bits */
static bit P57 @0x05@7:rpage 0;
static bit P56 @0x05@6:rpage 0;
static bit P55 @0x05@5:rpage 0;
static bit P54 @0x05@4:rpage 0;
static bit P53 @0x05@3:rpage 0;
static bit P52 @0x05@2:rpage 0;
static bit P51 @0x05@1:rpage 0;
static bit P50 @0x05@0:rpage 0;
/* R6 bits */
static bit P67 @0x06@7:rpage 0;
static bit P66 @0x06@6:rpage 0;
static bit P65 @0x06@5:rpage 0;
static bit P64 @0x06@4:rpage 0;
static bit P63 @0x06@3:rpage 0;
static bit P62 @0x06@2:rpage 0;
static bit P61 @0x06@1:rpage 0;
static bit P60 @0x06@0:rpage 0;
/* ISR bits */
static bit EXIF @0x0F@2:rpage 0; // External interrupt flag
static bit ICIF @0x0F@1:rpage 0; // Port 6 input status change interrupt flag
static bit TCIF @0x0F@0:rpage 0; // TCC overflow interrupt flag
/* R10~R2F General-purpose registers */
/*static unsigned int R10 @0x10:rpage 0;
static unsigned int R11 @0x11:rpage 0;
static unsigned int R12 @0x12:rpage 0;
static unsigned int R13 @0x13:rpage 0;
static unsigned int R14 @0x14:rpage 0;
static unsigned int R15 @0x15:rpage 0;
static unsigned int R16 @0x16:rpage 0;
static unsigned int R17 @0x17:rpage 0;
static unsigned int R18 @0x18:rpage 0;
static unsigned int R19 @0x19:rpage 0;
static unsigned int R1A @0x1A:rpage 0;
static unsigned int R1B @0x1B:rpage 0;
static unsigned int R1C @0x1C:rpage 0;
static unsigned int R1D @0x1D:rpage 0;
static unsigned int R1E @0x1E:rpage 0;
static unsigned int R1F @0x1F:rpage 0;
static unsigned int R20 @0x20:rpage 0;
static unsigned int R21 @0x21:rpage 0;
static unsigned int R22 @0x22:rpage 0;
static unsigned int R23 @0x23:rpage 0;
static unsigned int R24 @0x24:rpage 0;
static unsigned int R25 @0x25:rpage 0;
static unsigned int R26 @0x26:rpage 0;
static unsigned int R27 @0x27:rpage 0;
static unsigned int R28 @0x28:rpage 0;
static unsigned int R29 @0x29:rpage 0;
static unsigned int R2A @0x2A:rpage 0;
static unsigned int R2B @0x2B:rpage 0;
static unsigned int R2C @0x2C:rpage 0;
static unsigned int R2D @0x2D:rpage 0;
static unsigned int R2E @0x2E:rpage 0;
static unsigned int R2F @0x2F:rpage 0;*/
/*********Special Purpose Registers Define********************/
/* CONT bits */
/*static bit mINT @0x01@7:rpage 0;//
static bit TS @0x01@6:rpage 0;//
static bit TE @0x01@5:rpage 0;//
static bit PAB @0x01@4:rpage 0;//
static bit PSR2 @0x01@3:rpage 0;//
static bit PSR1 @0x01@1:rpage 0;//
static bit PSR0 @0x01@0:rpage 0;//*/
static io unsigned int P5CR @0x05:iopage 0; //Bit[n]="0", Set P5[n] as Output Pin, n=3~0
static io unsigned int P6CR @0x06:iopage 0; // Bit[n]= "0" , Set P6[n] as output pin, n=7~4,2~0
static io unsigned int PDCR @0x0B:iopage 0; // "1": Disable internal pull-dowm
static io unsigned int ODCR @0x0C:iopage 0; // Bit[n]= "1": Disable Open-Drain Function.n=7~4,2~0
static io unsigned int PHCR @0x0D:iopage 0; // Bit[n]= "1": Disable Pull High Function.n=7~4,2~0
static io unsigned int WDTCR @0x0E:iopage 0;
static io unsigned int IMR @0x0F:iopage 0; |