写COREUART
module uart_tx(clk, rst_n, txrdy, datain, wen, dataout);
input clk; // global clock input
input rst_n; // global reset input
input txrdy; // signs that transmitter is ready
input[7:0] datain;
output wen;
output dataout;
reg wen;
reg[7:0] dataout;
reg tx_busy;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0)
wen <= 1'b1;
else
begin
if (tx_busy)
wen <= 1'b1;
else
begin
wen <= 1'b0;
dataout <= datain;
end
end
end
always @(negedge clk)
begin
if (txrdy)
tx_busy <= 1'b0;
else
tx_busy <= 1'b1;
end
endmodule
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