Cortex-M0
Architecture ARMv6-M (Von Neumann)
ISA support Thumb®/ Thumb-2 technology*
Pipeline 3-stage
Dhrystone 0.9 DMIPS/MHz
Interrupts NMI + 1 to 32 physical interrupts
Interrupt latency 16 cycles
Sleep modes Integrated WFI and WFE instructions
Sleep & Deep Sleep Signals
Optional Retention Mode with Power Management Kit
Enhanced Instructions Single-cycle (32x32) multiply
Debug JTAG or Serial-Wire Debug ports
Cortex-M3 Features
Architecture ARMv7-M (Harvard)
ISA Support Thumb® / Thumb-2
Pipeline 3-stage + branch speculation
Dhrystone 1.25 DMIPS/MHz
Memory Protection Optional 8 region MPU with sub regions and background region
Interrupts Non-maskable Interrupt (NMI) + 1 to 240 physical interrupts
Interrupt Latency 12 cycles
Inter-Interrupt Latency 6 cycles
Interrupt Priority Levels 8 to 256 priority levels
Wake-up Interrupt Controller Up to 240 Wake-up Interrupts
Sleep Modes
Integrated WFI and WFE Instructions and Sleep On Exit capability.
Sleep & Deep Sleep Signals.
Optional Retention Mode with ARM Power Management Kit
Bit Manipulation Integrated Instructions & Bit Banding
Enhanced Instructions Hardware Divide (2-12 Cycles) & Single-Cycle (32x32) Multiply.
Debug Optional JTAG & Serial-Wire Debug Ports. Up to 8 Breakpoints and 4 Watchpoints.
Trace Optional Instruction Trace (ETM), Data Trace (DWT), and Instrumentation Trace (ITM)
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