Note
Use of the PC as the base register in the STC instruction is deprecated in ARMv7.
• Read the word-aligned PC value, that is, the address of the current instruction + 4, with
bits [1:0] forced to zero. The base register of LDC, LDR, LDRB, LDRD (pre-indexed, no write-back),
LDRH, LDRSB, and LDRSH instructions can be the word-aligned PC. This enables PC-relative data
addressing. In addition, some encodings of the ADD and SUB instructions permit their source
registers to be 0b1111 for the same purpose.
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