//-------------------------------------------------------------------------
// Step 1: ÅäÖÃSCUʱÖÓ
// PASSWD ---RM1.0 Page326
// CLKCR ---RM1.0 Page298
//-------------------------------------------------------------------------
SCU_GENERAL->PASSWD = 0x000000C0UL;
SCU_CLK->CLKCR = 0x3FF00400UL; // 8 MHz MCLK, 8 MHz PCLK
while((SCU_CLK->CLKCR)&0x40000000UL); // µÈ´ýVDDCµçѹÎȶ¨
SCU_GENERAL->PASSWD = 0x000000C3UL;
//-------------------------------------------------------------------------
// Step 2: ÊÂÇéÇëÇóÔ´ P2.8¡ª¡ªERU0_3B1 £» P2.9¡ª¡ªERU0_3B0
// ERU_EXISEL ---RM1.0 Page133
//-------------------------------------------------------------------------
WR_REG(ERU0->EXISEL, ERU_EXISEL_EXS3A_Msk, ERU_EXISEL_EXS3A_Pos, 1); //Ñ¡ÔñERU0_3A1ÊäÈë P2.7
WR_REG(ERU0->EXISEL, ERU_EXISEL_EXS3B_Msk, ERU_EXISEL_EXS3B_Pos, 1); //Ñ¡ÔñERU0_3B1ÊäÈë P2.8
WR_REG(ERU0->EXISEL, ERU_EXISEL_EXS3B_Msk, ERU_EXISEL_EXS3B_Pos, 0); //Ñ¡ÔñERU0_3B0ÊäÈë P2.9
//-------------------------------------------------------------------------
// Step 3: P2.1¸ßµçƽÆڼ䣬P2.5ÓÐϽµÑØʱ£¬ÔÚOGU0¶Ë¿Ú´¥·¢Âö³å
// ERU_EXICON ---RM1.0 Page135
//-------------------------------------------------------------------------
WR_REG(ERU0->EXICON[1], ERU_EXICON_SS_Msk, ERU_EXICON_SS_Pos, 0); //Ñ¡ÔñÊäÈëÐźÅ×éºÏ·½Ê½£ºÂß¼¡°Ó롱 A&B
WR_REG(ERU0->EXICON[1], ERU_EXICON_PE_Msk, ERU_EXICON_PE_Pos, 1); //ʹÄܲúÉú´¥·¢Âö³å
WR_REG(ERU0->EXICON[1], ERU_EXICON_RE_Msk, ERU_EXICON_RE_Pos, 0); //ÉÏÉýÑز»´¥·¢
WR_REG(ERU0->EXICON[1], ERU_EXICON_FE_Msk, ERU_EXICON_FE_Pos, 1); //ϽµÑØ´¥·¢
WR_REG(ERU0->EXICON[1], ERU_EXICON_OCS_Msk, ERU_EXICON_OCS_Pos, 0); //Ñ¡ÔñÔÚOGU0¶Ë¿Ú´¥·¢Âö³å
//-------------------------------------------------------------------------
// Step 4: ʹÄÜOGU0ÉϵÄÖжÏ
// EXOCON ---RM1.0 Page118
//-------------------------------------------------------------------------
WR_REG(ERU0->EXOCON[0], ERU_EXOCON_GP_Msk, ERU_EXOCON_GP_Pos, 1);
//-------------------------------------------------------------------------
// Step 5: ÅäÖÃIO¿Ú£¬ P2.1ºÍ P2.5 ÊäÈ룻P0.0Êä³ö
// PORT_IOCR0 ---RM1.0 Page1205
// PORT_IOCR4 ---RM1.0 Page1206
// PORT_PDISC ---RM1.0 Page1214
//-------------------------------------------------------------------------
// P0_1_set_mode(OUTPUT_PP_GP); //gpio¿Ú³õʼ»¯
// P0_6_set();
//
//
// P0_0_set_mode(OUTPUT_PP_GP); // ÅäÖÃP0.0 Êä³ö led
P2_8_enable_digital();
P2_8_set_mode(INPUT); // ÅäÖÃP2.8ÊäÈë
P2_9_enable_digital();
P2_9_set_mode(INPUT); // ÅäÖÃP2.9ÊäÈë
// P2_7_enable_digital();
// P2_7_set_mode(INPUT); // ÅäÖÃP2.7ÊäÈë
//
// P0_6_set_mode(OUTPUT_PP_GP); //led
//-------------------------------------------------------------------------
// Step 6: ÅäÖÃÖжÏ
// NVIC_ICPR ---RM1.0 Page112
// NVIC_ISER ---RM1.0 Page109
//-------------------------------------------------------------------------
NVIC_ClearPendingIRQ(ERU0_0_IRQn); //Çå³ý½ÚµãµÄµÈ´ý״̬
NVIC_EnableIRQ(ERU0_0_IRQn); //ʹÄܽڵãÖжÏÇëÇó |
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