这是主程序module test1(
input wire clk,
input wire rst,
input wire [7:0] in,
//output reg [3:0] cnt,
output reg [7:0] out
);
always @ (posedge clk or negedge rst)
begin
if(!rst)
begin
out <= 0;
end
else
begin
out <= in;
end
end
这是仿真tb
// Generate the stimulate
initial begin
clk = 1'b0;
rst = 1'b0;
in = 8'h00;
#40; rst = 1'b1;
#20; in = 8'b00001111;
#20; in = 8'h55;
#20; in = 8'h23;
#20; in = 8'h96;
#1000; $finish();
end
always
begin
#10 clk =~clk;
end
下面是仿真后的道德波形？为什么没有赋值过去呢？
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