CPLD模块输出自定义

只看该作者 · 2017-5-2 12:00

各位大神，如何用vel-HDL或者VHDL实现如下功能：一个模块的输出端口，初始为1，经过5个时钟周期后输出为0 ？？？

只看该作者 · 2017-5-15 17:45

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity load_A is
  PORT(
   clk_50 :IN  STD_LOGIC;  --输入主频
   pin_out :OUT STD_LOGIC --输出管脚
   );
end load_A;

architecture Behavioral of load_A is
SIGNAL output_reg:STD_LOGIC:='1';
BEGIN
PROCESS
VARIABLE cnt: INTEGER RANGE 0 to 500;
BEGIN
      WAIT UNTIL(RISING_EDGE(clk_50));
         IF cnt=50 THEN
            cnt:=0;
               output_reg<='0';
         ELSE
            cnt:=cnt+1;
         END IF;
      END PROCESS;
pin_out<=output_reg;
end Behavioral;

CPLD模块输出自定义

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