采样的时候PDF中说明输入阻抗只有100欧姆,采样电容需要吸收电流,所以前级的输出阻抗要越小越好。
source of the analog input voltage must be able to charge the input capacitance (24pF) to 16-bit level within 4.5 clock cycles。
是不是要在4.5个时钟周期内完成对24pF电容充电?
When the converter goes into the hold mode, or while it is in the power-down mode, the input impedance is greater than 1G欧姆.
这句话怎么理解??如果4.5个时钟周期内没有完成对它的采样,会进入power-down模式? |