本帖最后由 andyany 于 2010-9-17 14:27 编辑
作了一个串口发送。仿真出现负值。
顶层模块为——
module read_txd(clkin,addr_read
//,num2
);
input clkin;
output [ 7:0] addr_read;
//output [4:0]num2;
reg txd;
reg clk_bps;
reg [ 4:0] num = 5'd0;
reg [ 9:0] cnt = 10'd0;
reg [11:0] data_reg = 12'd0;
reg [ 7:0] addr_reg = 8'd0;
assign addr_read = addr_reg;
//assign num2 = num;
parameter period_cnt = 10'd2;
always @ (negedge clkin)
if(cnt == period_cnt)begin
cnt <= 10'd0;
clk_bps <= 1'b1; end
else begin
cnt <= cnt+10'd1;
clk_bps <= 1'b0; end
always @ (negedge clkin)
if (clk_bps)begin
num <= num + 5'd1;
case (num)
5'd0: txd <= 1'b1;
5'd1: txd <= 1'b0;
5'd2: txd <= data_reg[0];
5'd3: txd <= data_reg[1];
5'd4: txd <= data_reg[2];
5'd5: txd <= data_reg[3];
5'd6: txd <= data_reg[4];
5'd7: txd <= data_reg[5];
5'd8: txd <= data_reg[6];
5'd9: txd <= data_reg[7];
5'd10: txd <= 1'b1;
5'd11: txd <= 1'b0;
5'd12: txd <= data_reg[8];
5'd13: txd <= data_reg[9];
5'd14: txd <= data_reg[10];
5'd15: txd <= data_reg[11];
5'd16: txd <= 1'b0;
5'd17: txd <= 1'b0;
5'd18: txd <= 1'b0;
default: begin txd <= 1'b0;
if(addr_reg < 8'd166)
addr_reg <= addr_reg + 8'd1;
num <= 5'd0; end
endcase
end
endmodule
testbench为——
module test_v;
reg clkin;
wire [7:0] addr_read;
//wire [4:0] num2;
read_txd uut (
.clkin(clkin),
.addr_read(addr_read)
//.num2(num2)
);
initial
clkin = 0;
always #10 clkin = !clkin;
endmodule
结果地址递增到127之后便为-128，-127，-126。。。
如果把num引出，递增到15之后就变成-16，-15，-14，-13，0，1，2。。。地址递增的节点倒是对的。
不知问题出在哪了？
请大侠指导一下吧！先谢过！ |
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