module digital(clk,puls,en,s1,s2,led1,led2);
input clk,en,s1,s2;
output puls,led1,led2;
reg [8:0] cunt_s,cunt_on,cunt_off,temp_on,temp_off;
reg [2:0 ] cunt_m;
reg [23:0] clock_s;
reg led1,led2,clock;
wire s1,s2,en,clk;
reg puls,**;
always @(posedge clk)//--------------puls occur
begin
if(**==1'b1) begin
if(cunt_on==9'b100101100) begin
cunt_on<=9'b0;
puls<=1'b1;
**<=1'b0;
end
else
begin
cunt_on<=cunt_on+1'b1;
end
end
if(!**) begin
if(cunt_off==9'b100101100) begin
cunt_off<=9'b0;
puls<=1'b0;
**<=1'b1;
led1<=~led1;
end
else
begin
cunt_off<=cunt_off+1'b1;
end
end
end
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(clock_s==24'b100110001001011010000000) begin
clock<=~clock;
end
else
begin
clock_s<=clock_s+1'b1;
end
end
[email=always@(posedge]always@(posedge[/email] clk)
begin
if(s1==1'b0) begin
temp_on<=temp_on+9'b001111111;
temp_off<=temp_off;
led2<=1'b0;
end
else begin
temp_on<=temp_on;
temp_off<=temp_off;
led2<=1'b1;
end
end
endmodule
代码段如上 照理是S1按下低电平时led2为低电平发光，松开时因该不发光
仿真通过了，是s1低电平时LED2低电平，s1高电平时LED2为高电平
但是到了板子上，就不是那么了。开始为高电平不发光，当按键按下s1为低电平时
LED2发光，但是松开按键s1为高电平。照理LED熄灭，但实际情况是LED还发光
搞不清楚是为什么。
还有case语句后面只能对一个数据赋值吗 以前我用VHDL时可以加个，来对多个
signal赋值。verilog如何对同一个条件（case语句）下，对多个reg变量赋值。
以上还请高手指点一二 |
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