An EPP Data Read cycle is shown in Figure 5. The host de-asserts WRITE*, places the AD8-1 lines in a high impedance state, and asserts the DSTROBE* signal. The peripheral then drives the data byte on the AD8-1 lines and re-asserts WAIT* to indicate that the data byte is valid. The host will read the data lines when it sees the WAIT* unasserted, and then de-asserts DSTROBE*. The peripheral then places the AD8-1 lines in an high impedance state and asserts WAIT* to indicate it is ready for the next cycle.
我翻译的： 主机将WRITE*信号置高，将数据线AD8-1置高阻态，把信号线DSTROBE*拉低。然后，外设将数据写入AD8-1，把WAIT*信号拉低表示数据可读。
当检测到WAIT*信号为低时，主机将读取数据。然后将DSTROBE*信号拉高。外设然后将数据线AD8-1置为高阻态，再拉低WAIT*信号线，以示可以开始下一个周期。
我对其中红色标记的单词拿不准，希望大家指点一下，谢谢！ |
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