library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity bram_test1 is
port(
clk : in std_logic;
ram1_ad : in std_logic_vector(5 downto 0);
ram2_ad : in std_logic_vector(5 downto 0);
ram3_ad : in std_logic_vector(5 downto 0);
ram4_ad : in std_logic_vector(5 downto 0);
ram1_out : out std_logic_vector(7 downto 0);
ram2_out : out std_logic_vector(7 downto 0);
ram3_out : out std_logic_vector(7 downto 0);
ram4_out : out std_logic_vector(7 downto 0)
);
end bram_test1;
architecture Behavioral of bram_test1 is
type ram_30 is array(5 downto 0) of std_logic_vector(7 downto 0);
signal ram1 : ram_30;
signal ram2 : ram_30;
signal ram3 : ram_30;
signal ram4 : ram_30;
signal ram1_n : integer range 0 to 31;
signal ram2_n : integer range 0 to 31;
signal ram3_n : integer range 0 to 31;
signal ram4_n : integer range 0 to 31;
begin
read_ram : process(clk) is
begin
If clk='1' and clk'event then
ram1_n<=conv_INTEGER (ram1_ad);
ram2_n<=conv_INTEGER (ram2_ad);
ram3_n<=conv_INTEGER (ram3_ad);
ram4_n<=conv_INTEGER (ram4_ad);
ram1_out<=ram1(ram1_n);
ram2_out<=ram2(ram2_n);
ram3_out<=ram3(ram3_n);
ram4_out<=ram1(ram4_n);
end if;
end process read_ram;