我只会简单的例化，比如说顶层和底层的引脚都一样的那种
下面的图我就不会了![]()
我自己的例化程序，编译不成功，希望大家可以帮忙下
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(
clk,reset :in std_logic;
time_out :out std_logic
);
end entity;
architecture rtl of clock is
component time_ms is
port(
clk ,reset :in std_logic;
ms_out :out std_logic
);
end component;
component time_sec is
port(
clk ,reset :in std_logic;
ms_in :in std_logic;
sec_out :out std_logic
);
end component;
component time_min is
port(
clk ,reset :in std_logic;
sec_in :in std_logic;
min_out :out std_logic
);
end component;
component time_hour is
port(
clk ,reset :in std_logic;
min_in :in std_logic;
hour_out :out std_logic
);
end component;
begin
u1:time_ms port map(clk=>clk,reset=>reset);
u2:time_sec port map(clk=>clk,reset=>reset,ms_in=>ms_out);
u3:time_min port map(clk=>clk,reset=>reset,sec_in=>sec_out);
u4:time_hour port map(clk=>clk,reset=>reset,hour_in=>min_hour,hour_out=>time_out);
end architecture;
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