FPGA控制ADC0809

只看该作者 · 2011-8-20 21:20

module ADC0809(clk,rst,eoc,data,start,oe,aclk,q);
input clk;
input rst;
input eoc;
input[7:0]data;
output start;
output oe;
output aclk;
output[7:0]q;
reg start,oe,aclk,temp;
reg[7:0]q;
reg[2:0]current_time,next_time;
reg[4:0]count;
[email=always@(posedge]always@(posedge[/email] clk or negedge rst)
begin
if(!rst)
  count<=0;
else if(count==15'd1000)
  begin
count<=0;
aclk=~aclk;
  end
else count<=count+1;
end
[email=always@(posedge]always@(posedge[/email] clk)current_time<=next_time;
parameter st0=3'd0;
parameter st1=3'd1;
parameter st2=3'd2;
parameter st3=3'd3;
parameter st4=3'd4;
parameter st5=3'd5;
parameter st6=3'd6;
always@(*)
begin
if(!rst)
  next_time<=st0;
case(current_time)
st0:
begin
  start<=0;oe<=0;temp<=0;
  next_time<=st1;
end
st1:
begin
  start<=0;oe<=0;temp<=0;
  next_time<=st2;
end
st2:
begin
  start<=1;oe<=0;temp<=0;
  next_time<=st3;
end
st3:
begin
  start<=0;oe<=0;temp<=0;
  if(eoc==1)
next_time<=st3;
  else next_time<=st4;
end
st4:
begin
  start<=0;oe<=0;temp<=0;
  if(eoc==0)
next_time<=st4;
  else next_time<=st5;
end
st5:
begin
  start<=0;oe<=1;temp<=0;
  next_time<=st6;
end
st6:
begin
  start<=0;oe<=1;temp<=1;
  next_time<=st0;
end
default:
begin
  start<=0;oe<=0;
  next_time<=st0;
end
endcase
end
[email=always@(posedge]always@(posedge[/email] temp)q<=8'd0;
endmodule
我把等到的数据传回单片机，但始终没反应，求助高手