昨晚一直在思考,关于上述两个选项的问题:
PreferredLanguage 和 VHDL Source Analysis Standard
总觉得不应该与PreferredLanguage这个选项有关,因为这个选项的意思是:首选描述语言
今早回办公室,重新调整选项:
PreferredLanguage = Verilog HDL (仍然采用系统默认选项)
编译通过!
Timing Summary:
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Speed Grade: -1
Minimum period: 7.481ns (Maximum Frequency: 133.672MHz)
Minimum input arrival time before clock: 3.860ns
Maximum output required time after clock: 8.043ns
Maximum combinational path delay: 2.788ns
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Process "Synthesize - XST" completed successfully
于是乎总结一下:是否13.2的模块描述所采用的VHDL IEEE标准提高到VHDL 200X了?严重怀疑! |