本帖最后由 youhm 于 2019-3-16 15:42 编辑
M058S开发板，使用BSP例程，想测试一下内部时钟HIRC PLL
修改PLLCON_SETTING CLK_PLLCON_50MHz_HIRC
屏蔽掉外部时钟使能，切换HCLK到PLL，时钟仍然是内部22M
取消屏蔽外部时钟使能及等待外部时钟稳定，则HCLK时钟能达到HIRC PLL设定的频率
请解惑，谢谢
#define PLLCON_SETTING CLK_PLLCON_50MHz_HIRC
#define PLL_CLOCK 50000000
//uint32_t ii;
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable Internal RC 22.1184MHz clock */
CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;
/* Waiting for Internal RC clock ready */
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk));
/* Switch HCLK clock source to Internal RC and and HCLK source divide 1 */
CLK->CLKSEL0 &= ~CLK_CLKSEL0_HCLK_S_Msk;
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HIRC;
CLK->CLKDIV &= ~CLK_CLKDIV_HCLK_N_Msk;
CLK->CLKDIV |= CLK_CLKDIV_HCLK(1);
//// /* Enable external XTAL 12MHz clock */
//// CLK->PWRCON |= CLK_PWRCON_XTL12M_EN_Msk;
//// /* Waiting for external XTAL clock ready */
//// while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk));
/* Set core clock as PLL_CLOCK from PLL */
CLK->PLLCON = PLLCON_SETTING;
while(!(CLK->CLKSTATUS & CLK_CLKSTATUS_PLL_STB_Msk));
CLK->CLKSEL0 &= (~CLK_CLKSEL0_HCLK_S_Msk);
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_PLL;
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