FPGA 基础知识笔记1

只看该作者 · 2020-5-18 14:18

只看该作者 · 2020-5-21 16:03

本帖最后由 andy520520 于 2020-5-21 16:29 编辑

那位朋友看下，要怎么才能让LED在上电不亮，现在的情况是上电全亮，
然后才一个一个的输出

module led_water(led,clk);
      output[3:0]led;
      input clk;
      reg[3:0] led;
      reg[25:0] counter;
reg[3:0] state;
always@(posedge clk)
      begin
            counter<=counter+1;
            if(counter==26'd50000000)
               begin
            /*
                     led<=led<<1;
                     counter<=0;
                     if(led==8'b0000)
                     led<=8'b1111;
                     */
                        counter<=0;
                     case (state)


                                             4'b0000: begin
                                                                                    led <= 4'b1110;
                                                                                    state <= 4'b0001;
                                                                              end
                                             4'b00001:       begin
                                                                                    led <= 4'b1101;
                                                                                    state <= 4'b0010;
                                                                              end
                                             4'b0010:             begin
                                                                                    led <= 4'b1011;
                                                                                    state <= 4'b0011;
                                                                  end
                                             4'b0011:             begin
                                                                                    led <= 4'b0111;
                                                                                    state <= 4'b0000;
                                                                        end
                                             default:             state <= 4'b0000;

                     endcase

               end

      end
endmodule

FPGA 基础知识笔记1

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