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<div align="left">/**
* @brief LCD FSMC &Auml;&pound;&Ecirc;&frac12;&Aring;&auml;&Ouml;&Atilde;
* @param &Icirc;&THORN;
* @retval &Icirc;&THORN;
*/
void LCD_FSMC_Config(void)
{
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
FSMC_NORSRAMTimingInitTypeDef p;
p.FSMC_AddressSetupTime = 0x02; //&micro;&Oslash;&Ouml;·&frac12;¨&Aacute;&cent;&Ecirc;±&frac14;&auml;
p.FSMC_AddressHoldTime = 0x00; //&micro;&Oslash;&Ouml;·±&pound;&sup3;&Ouml;&Ecirc;±&frac14;&auml;
p.FSMC_DataSetupTime = 0x05; //&Ecirc;&yacute;&frac34;&Yacute;&frac12;¨&Aacute;&cent;&Ecirc;±&frac14;&auml;
p.FSMC_BusTurnAroundDuration = 0x00;
p.FSMC_CLKDivision = 0x00;
p.FSMC_DataLatency = 0x00;
p.FSMC_AccessMode = FSMC_AccessMode_B; // &Ograve;&raquo;°&atilde;&Ecirc;&sup1;&Oacute;&Atilde;&Auml;&pound;&Ecirc;&frac12;B&Agrave;&acute;&iquest;&Oslash;&Ouml;&AElig;LCD
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_NOR;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
/* &Ecirc;&sup1;&Auml;&Uuml; FSMC Bank1_SRAM Bank */
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
} |