库函数之内核时钟配置函数解读

/**

  * [url=home.php?mod=space&uid=247401]@brief[/url]      Set HCLK frequency 

  * @param[in]  u32Hclk is HCLK frequency

  * [url=home.php?mod=space&uid=266161]@return[/url]     HCLK frequency

  * [url=home.php?mod=space&uid=1543424]@Details[/url]    This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 25 MHz ~ 50 MHz.

  *             The register write-protection function should be disabled before using this function.

  */

uint32_t CLK_SetCoreClock(uint32_t u32Hclk)

{

    uint32_t u32HIRCSTB;



    /* Read HIRC clock source stable flag */    

    u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;        

    

    /* The range of u32Hclk is 25 MHz ~ 50 MHz */    

    if(u32Hclk > FREQ_50MHZ)

        u32Hclk = FREQ_50MHZ;

    else if(u32Hclk < FREQ_25MHZ)

        u32Hclk = FREQ_25MHZ;



    /* Switch HCLK clock source to HIRC clock for safe */

    CLK->PWRCON |= CLK_PWRCON_OSC22M_EN_Msk;

    CLK_WaitClockReady(CLK_CLKSTATUS_OSC22M_STB_Msk);  

    CLK->CLKSEL0 |= CLK_CLKSEL0_HCLK_S_HIRC;

    CLK->CLKDIV &= (~CLK_CLKDIV_HCLK_N_Msk);    

    

    /* Configure PLL setting if HXT clock is stable */

    if(CLK->CLKSTATUS & CLK_CLKSTATUS_XTL12M_STB_Msk)

        u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HXT, u32Hclk);



    /* Configure PLL setting if HXT clock is not stable */    

    else

    {

        u32Hclk = CLK_EnablePLL(CLK_PLLCON_PLL_SRC_HIRC, u32Hclk);

        

        /* Read HIRC clock source stable flag */    

        u32HIRCSTB = CLK->CLKSTATUS & CLK_CLKSTATUS_OSC22M_STB_Msk;            

    }



    /* Select HCLK clock source to PLL */    

    CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));



    /* Disable HIRC if HIRC is disabled before setting core clock */

    if( u32HIRCSTB == 0 )

        CLK->PWRCON &= ~CLK_PWRCON_OSC22M_EN_Msk;      

    

    return u32Hclk;

}