NUC029读取片内VBG电压

玛尼玛尼哄 · 2020-7-28 20:59

本帖最后由玛尼玛尼哄于 2020-7-28 21:11 编辑

这个芯片比较特殊，我用的是SGE的开发板，所以必须找到这个芯片手册，发现每个子系的ADC都不同，所以没法参考其他型号的，在DVD大礼包找到了手册。

在ADC通道选择上可以从0到19,29到31

TRM_NUC029xGE_Series_EN_Rev1.01.pdf (10.22 MB, 下载次数: 0)

2020-7-28 21:11 上传

点击文件名下载附件

其中0到19是外部测量，29到31是内部
ADC Data Registers (ADC_ADDRx x = 0~19, 29~31)

于是我知道怎么做了

/****************************************************************************
* [url=home.php?mod=space&uid=288409]@file[/url] main.c
* [url=home.php?mod=space&uid=895143]@version[/url] V3.0
* $Revision: 3 $
* $Date: 17/05/04 1:15p $
* [url=home.php?mod=space&uid=247401]@brief[/url] Perform A/D Conversion with ADC single cycle scan mode.
* @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
*
******************************************************************************/
#include <stdio.h>
#include "NUC029xGE.h"
#define PLL_CLOCK 72000000
/*---------------------------------------------------------------------------------------------------------*/
/* Define Function Prototypes */
/*---------------------------------------------------------------------------------------------------------*/
void SYS_Init(void);
void UART0_Init(void);
void AdcVBG(void);
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock (Internal RC 22.1184MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Waiting for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Select HCLK clock source as HIRC and and HCLK clock divider as 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Enable HXT clock (external XTAL 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Waiting for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Waiting for PLL clock ready */
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Enable ADC module clock */
CLK_EnableModuleClock(ADC_MODULE);
/* Select UART module clock source as HXT and UART module clock divider as 1 */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
/* ADC clock source is 22.1184MHz, set divider to 7, ADC clock is 22.1184/7 MHz */
CLK_SetModuleClock(ADC_MODULE, CLK_CLKSEL1_ADCSEL_HIRC, CLK_CLKDIV0_ADC(7));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set multi-function pins for UART0 RXD and TXD */
SYS->GPA_MFPL &= ~(SYS_GPA_MFPL_PA2MFP_Msk | SYS_GPA_MFPL_PA3MFP_Msk);
SYS->GPA_MFPL |= (SYS_GPA_MFPL_PA3MFP_UART0_RXD | SYS_GPA_MFPL_PA2MFP_UART0_TXD);
}
/*---------------------------------------------------------------------------------------------------------*/
/* Init UART */
/*---------------------------------------------------------------------------------------------------------*/
void UART0_Init()
{
/* Reset IP */
SYS_ResetModule(UART0_RST);
/* Configure UART0 and set UART0 Baudrate */
UART_Open(UART0, 115200);
}
/*---------------------------------------------------------------------------------------------------------*/
/* Function: AdcSingleCycleScanModeTest */
/* */
/* Parameters: */
/* None. */
/* */
/* Returns: */
/* None. */
/* */
/* Description: */
/* ADC single cycle scan mode test. */
/*---------------------------------------------------------------------------------------------------------*/
void AdcVBG()
{
int32_t i32ConversionData;
printf("\n");
printf("+----------------------------------------------------------------------+\n");
printf("| ADC VBG |\n");
printf("+----------------------------------------------------------------------+\n");
while(1)
{
printf("\n\nSelect input mode:\n");
printf(" [1] Single end input (channel 29 VBG)\n");
{
/* Set the ADC operation mode as single-cycle, input mode as single-end and
enable the analog input channel 29 */
ADC_Open(ADC, ADC_ADCR_DIFFEN_SINGLE_END, ADC_ADCR_ADMD_SINGLE_CYCLE, BIT29);
/* Power on ADC module */
ADC_POWER_ON(ADC);
/* Clear the A/D interrupt flag for safe */
ADC_CLR_INT_FLAG(ADC, ADC_ADF_INT);
/* Start A/D conversion */
ADC_START_CONV(ADC);
/* Wait conversion done */
while(!ADC_GET_INT_FLAG(ADC, ADC_ADF_INT)){}
{
i32ConversionData = ADC_GET_CONVERSION_DATA(ADC, 29);
printf("Conversion result of channel %d: 0x%X (%d)\n", 29, i32ConversionData, i32ConversionData);
}
printf("\n--按任意键进入下一次测试--\n");
getchar();
}
}
}
/*---------------------------------------------------------------------------------------------------------*/
/* MAIN function */
/*---------------------------------------------------------------------------------------------------------*/
int main(void)
{
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, IP clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
/*---------------------------------------------------------------------------------------------------------*/
/* SAMPLE CODE */
/*---------------------------------------------------------------------------------------------------------*/
printf("\nSystem clock rate: %d Hz", SystemCoreClock);
/* Single cycle scan mode test */
AdcVBG();
/* Disable ADC module */
ADC_Close(ADC);
/* Disable ADC IP clock */
CLK_DisableModuleClock(ADC_MODULE);
/* Disable External Interrupt */
NVIC_DisableIRQ(ADC_IRQn);
printf("\nExit ADC sample code\n");
while(1);
}
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

复制代码

玛尼玛尼哄 · 2020-7-28 20:59

测试结果

System clock rate: 72000000 Hz
+----------------------------------------------------------------------+
| ADC VBG |
+----------------------------------------------------------------------+
Select input mode:
[1] Single end input (channel 29 VBG)
Conversion result of channel 29: 0x6A5 (1701)
--按任意键进入下一次测试--
Select input mode:
[1] Single end input (channel 29 VBG)
Conversion result of channel 29: 0x669 (1641)
--按任意键进入下一次测试--
Select input mode:
[1] Single end input (channel 29 VBG)
Conversion result of channel 29: 0x66A (1642)
--按任意键进入下一次测试--
Select input mode:
[1] Single end input (channel 29 VBG)
Conversion result of channel 29: 0x66A (1642)
--按任意键进入下一次测试--
Select input mode:
[1] Single end input (channel 29 VBG)
Conversion result of channel 29: 0x66A (1642)
--按任意键进入下一次测试--

复制代码

玛尼玛尼哄 · 2020-7-28 21:00

观察，第一次测试不准，而第二次接近稳定，第三次开始稳定不变了，说明前两次可能不准需要丢弃。

玛尼玛尼哄 · 2020-7-28 21:01

又进行了测试，发现也就第一次不准，后面都是准的，只需要丢弃第一次启动时候的值即可，大家可以注意下。

玛尼玛尼哄 · 2020-7-28 21:07

不过改成30发现有问题，在查。

玛尼玛尼哄 · 2020-7-28 21:10

根据计算VBG应该是1.2V左右，因为手册没有给出所以不是很清楚，不知道数据手册有没有，一会儿去找找。

玛尼玛尼哄 · 2020-7-28 21:14

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